Lines Matching +full:0 +full:x70000
64 #define ALT_CPU_BIG_ENDIAN 0
65 #define ALT_CPU_BREAK_ADDR 0x00200820
69 #define ALT_CPU_CPU_ID_VALUE 0x00000000
71 #define ALT_CPU_DATA_ADDR_WIDTH 0x1c
72 #define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
76 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
77 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
78 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
83 #define ALT_CPU_HARDWARE_MULX_PRESENT 0
94 #define ALT_CPU_INST_ADDR_WIDTH 0x1c
96 #define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
98 #define ALT_CPU_RESET_ADDR 0x00000000
106 #define NIOS2_BIG_ENDIAN 0
107 #define NIOS2_BREAK_ADDR 0x00200820
111 #define NIOS2_CPU_ID_VALUE 0x00000000
113 #define NIOS2_DATA_ADDR_WIDTH 0x1c
114 #define NIOS2_DCACHE_BYPASS_MASK 0x80000000
118 #define NIOS2_EXCEPTION_ADDR 0x00400020
119 #define NIOS2_FLASH_ACCELERATOR_LINES 0
120 #define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
124 #define NIOS2_HARDWARE_MULX_PRESENT 0
135 #define NIOS2_INST_ADDR_WIDTH 0x1c
136 #define NIOS2_NUM_OF_SHADOW_REG_SETS 0
138 #define NIOS2_RESET_ADDR 0x00000000
169 #define ALT_LOG_PORT_BASE 0x0
172 #define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
176 #define ALT_STDERR_BASE 0x201000
182 #define ALT_STDIN_BASE 0x201000
188 #define ALT_STDOUT_BASE 0x201000
202 #define A_16550_UART_0_BASE 0x100000
205 #define A_16550_UART_0_FIO_HWFC 0
206 #define A_16550_UART_0_FIO_SWFC 0
209 #define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
221 #define EXT_FLASH_AVL_CSR_BASE 0x100240
224 #define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
225 #define EXT_FLASH_AVL_CSR_IS_EPCS 0
241 #define EXT_FLASH_AVL_MEM_BASE 0x8000000
245 #define EXT_FLASH_AVL_MEM_IS_EPCS 0
272 #define I2C_0_BASE 0x100200
276 #define I2C_0_IRQ_INTERRUPT_CONTROLLER_ID 0
280 #define I2C_0_USE_AV_ST 0
289 #define JTAG_UART_0_BASE 0x201000
290 #define JTAG_UART_0_IRQ 0
291 #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
307 #define LED_BASE 0x1002e0
308 #define LED_BIT_CLEARING_EDGE_REGISTER 0
309 #define LED_BIT_MODIFYING_OUTPUT_REGISTER 0
310 #define LED_CAPTURE 0
312 #define LED_DO_TEST_BENCH_WIRING 0
313 #define LED_DRIVEN_SIM_VALUE 0
316 #define LED_HAS_IN 0
318 #define LED_HAS_TRI 0
323 #define LED_RESET_VALUE 0
334 #define MSGDMA_0_CSR_BASE 0x1002c0
337 #define MSGDMA_0_CSR_CHANNEL_ENABLE 0
338 #define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0
343 #define MSGDMA_0_CSR_DMA_MODE 0
344 #define MSGDMA_0_CSR_ENHANCED_FEATURES 0
345 #define MSGDMA_0_CSR_ERROR_ENABLE 0
346 #define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0
349 #define MSGDMA_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
354 #define MSGDMA_0_CSR_PACKET_ENABLE 0
355 #define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0
356 #define MSGDMA_0_CSR_PREFETCHER_ENABLE 0
357 #define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0
360 #define MSGDMA_0_CSR_STRIDE_ENABLE 0
361 #define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0
372 #define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x1002f0
375 #define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0
376 #define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0
381 #define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 0
382 #define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0
383 #define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0
384 #define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0
392 #define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0
393 #define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0
394 #define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0
395 #define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0
398 #define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0
399 #define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0
410 #define ONCHIP_FLASH_0_CSR_BASE 0x200000
415 #define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0
417 #define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff
418 #define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0
420 #define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff
421 #define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000
423 #define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff
424 #define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000
426 #define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff
427 #define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000
428 #define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0
429 #define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff
430 #define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff
441 #define ONCHIP_FLASH_0_DATA_BASE 0x0
446 #define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0
448 #define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff
449 #define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0
451 #define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff
452 #define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000
454 #define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff
455 #define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000
457 #define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff
458 #define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000
459 #define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0
460 #define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff
461 #define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff
472 #define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
473 #define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
474 #define ONCHIP_MEMORY2_0_BASE 0x400000
476 #define ONCHIP_MEMORY2_0_DUAL_PORT 0
479 #define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0
484 #define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
487 #define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
501 #define SPI_0_BASE 0x100280
504 #define SPI_0_CLOCKPOLARITY 0
510 #define SPI_0_EXTRADELAY 0
511 #define SPI_0_INSERT_SYNC 0
513 #define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
515 #define SPI_0_LSBFIRST 0
532 #define SYSID_BASE 0x100300
533 #define SYSID_ID 0
548 #define TIMER_0_ALWAYS_RUN 0
549 #define TIMER_0_BASE 0x1002a0
551 #define TIMER_0_FIXED_PERIOD 0
554 #define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
560 #define TIMER_0_RESET_OUTPUT 0
564 #define TIMER_0_TIMEOUT_PULSE_OUTPUT 0