Lines Matching +full:board +full:- +full:schema

4 # Copyright (c) 2018-2022 Intel Corporation
7 # SPDX-License-Identifier: Apache-2.0
30     def is_runnable(self) -> bool:
46     Maps directly to BOARD when building"""
49         os.path.join(ZEPHYR_BASE, "scripts", "schemas", "twister", "platform-schema.yaml")
63         # if no RAM size is specified by the board, take a default of 128K
70         # if no flash size is specified by the board, take a default of 512K
76         self.tier = -1
88     def load(self, board, target, aliases, data):  argument
89         """Load the platform data from the board data and target data
90         board: the board object as per the zephyr build system
91         target: the target name of the board as per the zephyr build system
98         # Get data for various targets and use the main board data as a
100         # provded in the main twister configuration for this board.
112         # if no RAM size is specified by the board, take a default of 128K
114         # if no flash size is specified by the board, take a default of 512K
132         self.vendor = board.vendor
152           # toolchain ("zephyr", "cross-compile", "xtools" options) and for some targets we haven't
155           # Instead for 'arc' we rely on 'toolchain' option in board yaml configuration.
157           "arm64": ["zephyr", "cross-compile"],
160           "riscv": ["zephyr", "cross-compile"],
165           # that is supported on all board targets for xtensa.
179     def simulator_by_name(self, sim_name: str | None) -> Simulator | None: