Lines Matching refs:node
682 node: 'Node'
738 node: 'Node'
776 node: 'Node'
817 node: 'Node'
849 node: 'Node'
1092 return {name: self.edt._node2enode[node]
1093 for name, node in self._node.nodes.items()}
1095 def child_index(self, node) -> int: argument
1109 return self._child2index[node.path]
1158 return [alias for alias, node in self._node.dt.alias2node.items()
1159 if node is self._node]
1247 node=self, controller=controller,
1497 node = self._node
1498 prop = node.props.get(name)
1539 "('{0};')".format(name, node, binding_path, prop)
1562 return [self.edt._node2enode[node] for node in prop.to_nodes()]
1609 node = self._node
1613 if "ranges" not in node.props:
1616 raw_child_address_cells = node.props.get("#address-cells")
1617 parent_address_cells = _address_cells(node)
1622 raw_child_size_cells = node.props.get("#size-cells")
1632 if len(node.props["ranges"].value) == 0:
1640 for raw_range in _slice(node, "ranges", 4*entry_cells,
1672 node = self._node
1676 if "reg" not in node.props:
1679 address_cells = _address_cells(node)
1680 size_cells = _size_cells(node)
1682 for raw_reg in _slice(node, "reg", 4*(address_cells + size_cells),
1688 addr = _translate(to_num(raw_reg[:4*address_cells]), node)
1702 _add_names(node, "reg", self.regs)
1707 node = self._node
1710 pinctrl_props = [prop for name, prop in node.props.items()
1725 node=self,
1727 conf_nodes=[self.edt._node2enode[node]
1728 for node in prop.to_nodes()]))
1730 _add_names(node, "pinctrl", self.pinctrls)
1735 node = self._node
1739 for controller_node, data in _interrupts(node):
1743 node=self, controller=controller,
1747 _add_names(node, "interrupt", self.interrupts)
1812 _map_phandle_array_entry(prop.node, controller_node,
1818 node=self, controller=controller,
2049 node = prop.to_path()
2054 ret[name] = self._node2enode[node]
2144 def _process_properties(self, node: Node) -> None:
2149 self._process_properties_r(node, node)
2159 for node in self.nodes:
2161 if not node.parent:
2162 self._graph.add_node(node)
2165 for child in node.children.values():
2166 self._graph.add_edge(child, node)
2168 self._process_properties(node)
2276 node = Node(dt_node, self, self._fixed_partitions_no_bus)
2277 self.nodes.append(node)
2278 self._node2enode[dt_node] = node
2280 for node in self.nodes:
2285 node._init_crossrefs(
2292 for node in self.nodes:
2294 if (node.regs and node.regs[0].addr != node.unit_addr and
2295 not node.is_pci_device):
2303 for node in self.nodes:
2304 for label in node.labels:
2305 self.label2node[label] = node
2307 for compat in node.compats:
2308 if node.status == "okay":
2309 self.compat2okay[compat].append(node)
2311 self.compat2notokay[compat].append(node)
2331 elif node.path != '/':
2347 node = nodeset[0]
2348 self.dep_ord2node[node.dep_ordinal] = node
2373 for node in self.nodes:
2374 if 'compatible' not in node.props:
2377 compatibles = node.props['compatible'].val
2451 for node in dt.node_iter()
2452 if "compatible" in node.props
2453 for compat in node.props["compatible"].to_strings()}
2641 def _binding_include(loader, node): argument
2645 if isinstance(node, yaml.ScalarNode):
2647 return [loader.construct_scalar(node)]
2649 if isinstance(node, yaml.SequenceNode):
2651 return loader.construct_sequence(node)
2740 def _translate(addr: int, node: dtlib_Node) -> int:
2745 if not node.parent or "ranges" not in node.parent.props:
2749 if not node.parent.props["ranges"].value:
2756 return _translate(addr, node.parent)
2759 child_address_cells = _address_cells(node)
2760 parent_address_cells = _address_cells(node.parent)
2761 child_size_cells = _size_cells(node)
2766 for raw_range in _slice(node.parent, "ranges", 4*entry_cells,
2782 return _translate(parent_addr + addr - child_addr, node.parent)
2788 def _add_names(node: dtlib_Node, names_ident: str, objs: Any) -> None:
2802 if full_names_ident in node.props:
2803 names = node.props[full_names_ident].to_strings()
2824 node: Optional[dtlib_Node] = start_node
2826 while node:
2827 if "interrupt-parent" in node.props:
2828 return node.props["interrupt-parent"].to_node()
2829 node = node.parent
2835 def _interrupts(node: dtlib_Node) -> List[Tuple[dtlib_Node, bytes]]:
2842 if "interrupts-extended" in node.props:
2843 prop = node.props["interrupts-extended"]
2851 ret.append(_map_interrupt(node, iparent, spec))
2854 if "interrupts" in node.props:
2858 iparent = _interrupt_parent(node)
2861 return [_map_interrupt(node, iparent, raw)
2862 for raw in _slice(node, "interrupts", 4*interrupt_cells,
2880 def own_address_cells(node): argument
2885 address_cells = node.props.get("#address-cells")
2891 def spec_len_fn(node): argument
2894 return own_address_cells(node) + _interrupt_cells(node)
2914 def spec_len_fn(node): argument
2916 if prop_name not in node.props:
2919 return node.props[prop_name].to_num()
3061 def _raw_unit_addr(node: dtlib_Node) -> bytes:
3065 if 'reg' not in node.props:
3069 addr_len = 4*_address_cells(node)
3071 if len(node.props['reg'].value) < addr_len:
3075 return node.props['reg'].value[:addr_len]
3136 node = prop.node.dt.phandle2node.get(phandle)
3137 if not node:
3143 if full_n_cells_name not in node.props:
3146 n_cells = node.props[full_n_cells_name].to_num()
3150 res.append((node, raw[:4*n_cells]))
3156 def _address_cells(node: dtlib_Node) -> int:
3160 assert node.parent
3162 if "#address-cells" in node.parent.props:
3163 return node.parent.props["#address-cells"].to_num()
3167 def _size_cells(node: dtlib_Node) -> int:
3171 assert node.parent
3173 if "#size-cells" in node.parent.props:
3174 return node.parent.props["#size-cells"].to_num()
3178 def _interrupt_cells(node: dtlib_Node) -> int:
3182 if "#interrupt-cells" not in node.props:
3184 return node.props["#interrupt-cells"].to_num()
3187 def _slice(node: dtlib_Node,
3191 return _slice_helper(node, prop_name, size, size_hint, EDTError)
3204 for node in dt.node_iter():
3205 if "status" in node.props:
3207 status_val = node.props["status"].to_string()
3218 ranges_prop = node.props.get("ranges")