26 	LOG_INF("MEC152x PCR registers");  in pcr_clock_regs()
28 	LOG_INF("PCR Power Reset Status register(bit[10] is 32K_ACTIVE) = 0x%x", r);  in pcr_clock_regs()
31 	LOG_INF("PCR Oscillator ID register(bit[8]=PLL Lock) = 0x%x", r);  in pcr_clock_regs()
34 	LOG_INF("PCR Processor Clock Control register = 0x%x", r);  in pcr_clock_regs()
37 	LOG_INF("PCR Slow Clock Control register = 0x%x", r);  in pcr_clock_regs()
45 	LOG_INF("MEC152x VBAT Clock registers");  in vbat_clock_regs()
46 	LOG_INF("ClockEnable = 0x%08x", cken);  in vbat_clock_regs()
48 		LOG_INF("32KHz clock source is XTAL");  in vbat_clock_regs()
50 			LOG_INF("XTAL configured for single-ended using XTAL2 pin"  in vbat_clock_regs()
53 			LOG_INF("XTAL configured for parallel resonant crystal circuit on"  in vbat_clock_regs()
57 		LOG_INF("32KHz clock source is the Internal Silicon 32KHz OSC");  in vbat_clock_regs()
60 		LOG_INF("32KHz clock domain uses the 32KHZ_IN pin(GPIO_0165 F1)");  in vbat_clock_regs()
62 		LOG_INF("32KHz clock domain uses the 32KHz clock source");  in vbat_clock_regs()
65 	LOG_INF("32KHz trim = 0x%08x", vbr->CKK32_TRIM);  in vbat_clock_regs()
73 	LOG_INF("MEC152x VBAT Power-Fail-Reset-Status = 0x%x", pfrs);  in vbat_power_fail()
76 		LOG_INF("WARNING: VBAT POR. Clock control register settings lost during"  in vbat_power_fail()
88 		LOG_INF("PLL 32K clock source is Internal Silicon OSC(VTR)");  in print_pll_clock_src()
90 		LOG_INF("PLL 32K clock source is XTAL input(VTR)");  in print_pll_clock_src()
92 		LOG_INF("PLL 32K clock source is 32KHZ_IN pin(VTR)");  in print_pll_clock_src()
94 		LOG_INF("PLL 32K clock source is OFF. PLL disabled. Running on Ring OSC");  in print_pll_clock_src()
103 		LOG_INF("Periph 32K clock source is InternalOSC(VTR) and InternalOSC(VBAT)");  in print_periph_clock_src()
105 		LOG_INF("Periph 32K clock source is XTAL(VTR) and XTAL(VBAT)");  in print_periph_clock_src()
107 		LOG_INF("Periph 32K clock source is 32KHZ_PIN(VTR) and InternalOSC(VBAT)");  in print_periph_clock_src()
109 		LOG_INF("Periph 32K clock source is 32KHZ_PIN fallback to XTAL when VTR is off");  in print_periph_clock_src()
119 	LOG_INF("MEC172x PCR registers");  in pcr_clock_regs()
123 	LOG_INF("PCR Power Reset Status register(b[10] is 32K_ACTIVE) = 0x%x", r);  in pcr_clock_regs()
126 	LOG_INF("PCR Oscillator ID register(bit[8]=PLL Lock) = 0x%x", r);  in pcr_clock_regs()
129 	LOG_INF("PCR Processor Clock Control register = 0x%x", r);  in pcr_clock_regs()
132 	LOG_INF("PCR Slow Clock Control register = 0x%x", r);  in pcr_clock_regs()
135 	LOG_INF("PCR 32KHz Clock Monitor Pulse High Count register = 0x%x", r);  in pcr_clock_regs()
138 	LOG_INF("PCR 32KHz Clock Monitor Period Maximum Count register = 0x%x", r);  in pcr_clock_regs()
141 	LOG_INF("PCR 32KHz Clock Monitor Duty Cycle Variation register = 0x%x", r);  in pcr_clock_regs()
144 	LOG_INF("PCR 32KHz Clock Monitor Duty Cycle Variation Max register = 0x%x", r);  in pcr_clock_regs()
147 	LOG_INF("PCR 32KHz Clock Monitor Valid register = 0x%x", r);  in pcr_clock_regs()
150 	LOG_INF("PCR 32KHz Clock Monitor Valid Min register = 0x%x", r);  in pcr_clock_regs()
153 	LOG_INF("PCR 32KHz Clock Monitor Control register = 0x%x", r);  in pcr_clock_regs()
156 	LOG_INF("PCR 32KHz Clock Monitor Control Status register = 0x%x", r);  in pcr_clock_regs()
172 	LOG_INF("MEC172x VBAT Power-Fail-Reset-Status = 0x%x", pfrs);  in vbat_power_fail()
175 		LOG_INF("WARNING: VBAT POR. Clock control register settings"  in vbat_power_fail()
209 	LOG_INF("XEC Clock control driver sample");  in main()
218 	LOG_INF("32KHZ_IN is function 1 of GPIO 0165");  in main()
220 	LOG_INF("XEC GPIO 0165 Control = 0x%x", r);  in main()
222 	LOG_INF("Pin function = %u", r);  in main()
227 		LOG_INF("API get rate for %s", sys_clocks[i].name);  in main()
234 			LOG_INF("rate = %u", rate);  in main()