Lines Matching +full:mixed +full:- +full:mode

1 .. zephyr:code-sample:: clock-control-litex
3    :relevant-api: clock_control_interface
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25    :start-at: clk0: clock-controller@0 {
26    :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31    :start-at: clk1: clock-controller@1 {
32    :end-at: };
35 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
37    :start-at: clock0: clock@e0004800 {
38    :end-at: };
41 …aken when defining values for FPGA-specific configuration (parameters from ``litex,divclk-divide-m…
53 .. code-block:: c
96 .. code-block:: none
98   west build -b litex_vexriscv zephyr/samples/drivers/clock_control
105 .. code-block:: none
115   *** Booting Zephyr OS build zephyr-v2.2.0-2810-g1ca5dda196c3  ***
135 - :ref:`litex-vexriscv`