Lines Matching +full:90 +full:-
1 .. zephyr:code-sample:: clock-control-litex
3 :relevant-api: clock_control_interface
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25 :start-at: clk0: clock-controller@0 {
26 :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31 :start-at: clk1: clock-controller@1 {
32 :end-at: };
35 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
37 :start-at: clock0: clock@e0004800 {
38 :end-at: };
41 …aken when defining values for FPGA-specific configuration (parameters from ``litex,divclk-divide-m…
51 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
53 .. code-block:: c
61 .phase = 90
96 .. code-block:: none
98 west build -b litex_vexriscv zephyr/samples/drivers/clock_control
105 .. code-block:: none
115 *** Booting Zephyr OS build zephyr-v2.2.0-2810-g1ca5dda196c3 ***
122 [00:00:00.550,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set phase: 90 deg
127 CLKOUT0: get_status: rate:15000000 phase:90 duty:25
135 - :ref:`litex-vexriscv`