Lines Matching +full:2 +full:- +full:phase

1 .. zephyr:code-sample:: clock-control-litex
3    :relevant-api: clock_control_interface
11 … Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phase, frequency and dut…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25    :start-at: clk0: clock-controller@0 {
26    :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31    :start-at: clk1: clock-controller@1 {
32    :end-at: };
35 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
37    :start-at: clock0: clock@e0004800 {
38    :end-at: };
41 …2 clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100MHz, 0 degrees phase offse…
51 | This code will try to set on ``clk0`` frequency 50MHz, 90 degrees of phase offset and 75% duty cy…
53 .. code-block:: c
61 		.phase = 90
70 Clock output status (frequency, duty and phase offset) can be acquired with function ``clock_contro…
81 * Phase range,
82 * Setting frequency, duty and phase at once, then check clock status and rate,
91 Code is performed on 2 clock outputs with ``clkout_nr`` defined in ``LITEX_CLK_TEST_CLK1`` and ``LI…
96 .. code-block:: none
98   west build -b litex_vexriscv zephyr/samples/drivers/clock_control
105 .. code-block:: none
110   [00:00:00.320,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set phase: 0 deg
113   [00:00:00.440,000] <inf> CLK_CTRL_LITEX: CLKOUT1: set phase: 0 deg
115   *** Booting Zephyr OS build zephyr-v2.2.0-2810-g1ca5dda196c3  ***
122   [00:00:00.550,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set phase: 90 deg
127   CLKOUT0: get_status: rate:15000000 phase:90 duty:25
129   CLKOUT1: get_status: rate:15000000 phase:0 duty:75
135 - :ref:`litex-vexriscv`