Lines Matching +full:18 +full:- +full:50
3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
125 #define GPIO28_P18 TI_CC32XX_PINMUX(18U, 0U)
148 #define GPIO0_P50 TI_CC32XX_PINMUX(50U, 0U)
149 #define UART0_CTSN_P50 TI_CC32XX_PINMUX(50U, 12U)
150 #define MCAXR1_P50 TI_CC32XX_PINMUX(50U, 6U)
151 #define GT_CCP00_P50 TI_CC32XX_PINMUX(50U, 7U)
152 #define GSPI_CS_P50 TI_CC32XX_PINMUX(50U, 9U)
153 #define UART1_RTS_P50 TI_CC32XX_PINMUX(50U, 10U)
154 #define UART0_RTS_P50 TI_CC32XX_PINMUX(50U, 3U)
155 #define MCAXR0_P50 TI_CC32XX_PINMUX(50U, 4U)