Lines Matching full:x5
135 #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
149 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
162 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
174 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
186 #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
200 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
213 #define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
227 #define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5)
239 #define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
253 #define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5)
265 #define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
279 #define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5)
291 #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
305 #define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5)
317 #define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
331 #define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5)
343 #define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
357 #define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5)
370 #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
382 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
394 #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
407 #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
421 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
433 #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
447 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
460 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
472 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
485 #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
499 #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
514 #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
528 #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
540 #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
554 #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
566 #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
578 #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
590 #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
602 #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
614 #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
626 #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
638 #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
650 #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
662 #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
674 #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
686 #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
698 #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
712 #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
726 #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
741 #define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5)
755 #define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5)
767 #define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
781 #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
793 #define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
807 #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
820 #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
834 #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
848 #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
862 #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
876 #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
890 #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
904 #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
916 #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
928 #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
940 #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
952 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
964 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
976 #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
990 #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
1002 #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
1016 #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1028 #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
1042 #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1054 #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
1068 #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1081 #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
1095 #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1107 #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1121 #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1133 #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1147 #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1159 #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1173 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1185 #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1199 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1211 #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1225 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1238 #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
1252 #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1264 #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
1278 #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1290 #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
1304 #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1316 #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
1330 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1342 #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
1356 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1368 #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
1382 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1395 #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
1409 #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
1423 #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
1437 #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
1451 #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
1465 #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
1480 #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1492 #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1504 #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1516 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1528 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1540 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1553 #define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
1567 #define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
1581 #define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
1595 #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
1609 #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
1623 #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
1638 #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
1652 #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
1664 #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
1678 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1690 #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
1704 #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
1716 #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1730 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1742 #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
1756 #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
1768 #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1782 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1795 #define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5)
1809 #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1823 #define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5)
1837 #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
1851 #define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5)
1865 #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)