Lines Matching full:x6
132 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
144 #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
156 #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
170 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
183 #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
195 #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
207 #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
220 #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
234 #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
246 #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
260 #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
273 #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
285 #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
298 #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
312 #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
327 #define EUART0_RTS_PA6 SILABS_DBUS_EUART0_RTS(0x0, 0x6)
341 #define EUART0_RTS_PC6 SILABS_DBUS_EUART0_RTS(0x2, 0x6)
353 #define EUART0_TX_PA6 SILABS_DBUS_EUART0_TX(0x0, 0x6)
367 #define EUART0_TX_PC6 SILABS_DBUS_EUART0_TX(0x2, 0x6)
379 #define EUART0_CTS_PA6 SILABS_DBUS_EUART0_CTS(0x0, 0x6)
393 #define EUART0_CTS_PC6 SILABS_DBUS_EUART0_CTS(0x2, 0x6)
405 #define EUART0_RX_PA6 SILABS_DBUS_EUART0_RX(0x0, 0x6)
419 #define EUART0_RX_PC6 SILABS_DBUS_EUART0_RX(0x2, 0x6)
432 #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
446 #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
458 #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
472 #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
484 #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
496 #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
508 #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
520 #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
532 #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
544 #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
556 #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
568 #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
580 #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
592 #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
604 #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
616 #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
630 #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
644 #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
659 #define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6)
673 #define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6)
685 #define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
699 #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
711 #define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
725 #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
738 #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
752 #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
766 #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
780 #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
794 #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
808 #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
822 #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
834 #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
846 #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
858 #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
870 #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
882 #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
894 #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
908 #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
920 #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
934 #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
946 #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
960 #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
972 #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
986 #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
999 #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1013 #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1025 #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1039 #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1051 #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1065 #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1077 #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1091 #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1103 #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1117 #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1129 #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
1143 #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1156 #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
1170 #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1182 #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
1196 #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1208 #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
1222 #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1234 #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
1248 #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1260 #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
1274 #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1286 #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
1300 #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1313 #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
1327 #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
1341 #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
1355 #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
1369 #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
1383 #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
1398 #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1410 #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1422 #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1434 #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1446 #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1458 #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1471 #define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
1485 #define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
1499 #define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
1513 #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
1527 #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
1541 #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
1556 #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
1570 #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
1582 #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
1596 #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1608 #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
1622 #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
1634 #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1648 #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1660 #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
1674 #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
1686 #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1700 #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1713 #define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6)
1727 #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1741 #define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6)
1755 #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
1769 #define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6)
1783 #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)