Lines Matching +full:0 +full:x3

16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin)  SILABS_DBUS(port, pin, 4, 0, 0, 1)
21 #define SILABS_DBUS_PTI_DCLK(port, pin)   SILABS_DBUS(port, pin, 15, 1, 0, 1)
25 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
28 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
31 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
34 #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
36 #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
37 #define SILABS_DBUS_EUART0_RX(port, pin)  SILABS_DBUS(port, pin, 32, 0, 0, 3)
39 #define SILABS_DBUS_MODEM_ANT0(port, pin)        SILABS_DBUS(port, pin, 38, 1, 0, 1)
54 #define SILABS_DBUS_MODEM_DIN(port, pin)         SILABS_DBUS(port, pin, 38, 0, 0, 15)
56 #define SILABS_DBUS_PDM_CLK(port, pin)  SILABS_DBUS(port, pin, 56, 1, 0, 1)
57 #define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 56, 0, 0, 2)
58 #define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 56, 0, 0, 3)
60 #define SILABS_DBUS_PRS0_ASYNCH0(port, pin)  SILABS_DBUS(port, pin, 61, 1, 0, 1)
77 #define SILABS_DBUS_TIMER0_CC0(port, pin)   SILABS_DBUS(port, pin, 79, 1, 0, 1)
84 #define SILABS_DBUS_TIMER1_CC0(port, pin)   SILABS_DBUS(port, pin, 87, 1, 0, 1)
91 #define SILABS_DBUS_TIMER2_CC0(port, pin)   SILABS_DBUS(port, pin, 95, 1, 0, 1)
98 #define SILABS_DBUS_TIMER3_CC0(port, pin)   SILABS_DBUS(port, pin, 103, 1, 0, 1)
105 #define SILABS_DBUS_TIMER4_CC0(port, pin)   SILABS_DBUS(port, pin, 111, 1, 0, 1)
112 #define SILABS_DBUS_USART0_CS(port, pin)  SILABS_DBUS(port, pin, 119, 1, 0, 1)
117 #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 119, 0, 0, 2)
119 #define SILABS_DBUS_USART1_CS(port, pin)  SILABS_DBUS(port, pin, 127, 1, 0, 1)
124 #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 2)
126 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
127 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
128 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
129 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
130 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
131 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
132 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
133 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
134 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
135 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
136 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
137 #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
138 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
139 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
140 #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
141 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
142 #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
143 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
144 #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
145 #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
146 #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
147 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
148 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
149 #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
150 #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
151 #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
152 #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
153 #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
154 #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
155 #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
156 #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
157 #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
158 #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
159 #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
160 #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
161 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
162 #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
163 #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
164 #define CMU_CLKIN0_PC0  SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
165 #define CMU_CLKIN0_PC1  SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
166 #define CMU_CLKIN0_PC2  SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
167 #define CMU_CLKIN0_PC3  SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
168 #define CMU_CLKIN0_PC4  SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
169 #define CMU_CLKIN0_PC5  SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
170 #define CMU_CLKIN0_PC6  SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
171 #define CMU_CLKIN0_PC7  SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
172 #define CMU_CLKIN0_PD0  SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
173 #define CMU_CLKIN0_PD1  SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
174 #define CMU_CLKIN0_PD2  SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
175 #define CMU_CLKIN0_PD3  SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
177 #define PTI_DCLK_PC0   SILABS_DBUS_PTI_DCLK(0x2, 0x0)
178 #define PTI_DCLK_PC1   SILABS_DBUS_PTI_DCLK(0x2, 0x1)
179 #define PTI_DCLK_PC2   SILABS_DBUS_PTI_DCLK(0x2, 0x2)
180 #define PTI_DCLK_PC3   SILABS_DBUS_PTI_DCLK(0x2, 0x3)
181 #define PTI_DCLK_PC4   SILABS_DBUS_PTI_DCLK(0x2, 0x4)
182 #define PTI_DCLK_PC5   SILABS_DBUS_PTI_DCLK(0x2, 0x5)
183 #define PTI_DCLK_PC6   SILABS_DBUS_PTI_DCLK(0x2, 0x6)
184 #define PTI_DCLK_PC7   SILABS_DBUS_PTI_DCLK(0x2, 0x7)
185 #define PTI_DCLK_PD0   SILABS_DBUS_PTI_DCLK(0x3, 0x0)
186 #define PTI_DCLK_PD1   SILABS_DBUS_PTI_DCLK(0x3, 0x1)
187 #define PTI_DCLK_PD2   SILABS_DBUS_PTI_DCLK(0x3, 0x2)
188 #define PTI_DCLK_PD3   SILABS_DBUS_PTI_DCLK(0x3, 0x3)
189 #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
190 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
191 #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
192 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
193 #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
194 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
195 #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
196 #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
197 #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
198 #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
199 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
200 #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
201 #define PTI_DOUT_PC0   SILABS_DBUS_PTI_DOUT(0x2, 0x0)
202 #define PTI_DOUT_PC1   SILABS_DBUS_PTI_DOUT(0x2, 0x1)
203 #define PTI_DOUT_PC2   SILABS_DBUS_PTI_DOUT(0x2, 0x2)
204 #define PTI_DOUT_PC3   SILABS_DBUS_PTI_DOUT(0x2, 0x3)
205 #define PTI_DOUT_PC4   SILABS_DBUS_PTI_DOUT(0x2, 0x4)
206 #define PTI_DOUT_PC5   SILABS_DBUS_PTI_DOUT(0x2, 0x5)
207 #define PTI_DOUT_PC6   SILABS_DBUS_PTI_DOUT(0x2, 0x6)
208 #define PTI_DOUT_PC7   SILABS_DBUS_PTI_DOUT(0x2, 0x7)
209 #define PTI_DOUT_PD0   SILABS_DBUS_PTI_DOUT(0x3, 0x0)
210 #define PTI_DOUT_PD1   SILABS_DBUS_PTI_DOUT(0x3, 0x1)
211 #define PTI_DOUT_PD2   SILABS_DBUS_PTI_DOUT(0x3, 0x2)
212 #define PTI_DOUT_PD3   SILABS_DBUS_PTI_DOUT(0x3, 0x3)
214 #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
215 #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
216 #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
217 #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
218 #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
219 #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
220 #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
221 #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
222 #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
223 #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
224 #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
225 #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
226 #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
227 #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
228 #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
229 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
230 #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
231 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
232 #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
233 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
234 #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
235 #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
236 #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
237 #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
238 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
239 #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
240 #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
241 #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
242 #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
243 #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
244 #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
245 #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
246 #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
247 #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
248 #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
249 #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
250 #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
251 #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
252 #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
253 #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
254 #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
255 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
256 #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
257 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
258 #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
259 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
260 #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
261 #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
262 #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
263 #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
264 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
265 #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
267 #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
268 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
269 #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
270 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
271 #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
272 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
273 #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
274 #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
275 #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
276 #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
277 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
278 #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
279 #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
280 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
281 #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
282 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
283 #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
284 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
285 #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
286 #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
287 #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
288 #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
289 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
290 #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
292 #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
293 #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
294 #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
295 #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
296 #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
297 #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
298 #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
299 #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
300 #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
301 #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
302 #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
303 #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
304 #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
305 #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
306 #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
307 #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
308 #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
309 #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
310 #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
311 #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
312 #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
313 #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
314 #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
315 #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
316 #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
317 #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
318 #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
319 #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
321 #define EUART0_RTS_PA0 SILABS_DBUS_EUART0_RTS(0x0, 0x0)
322 #define EUART0_RTS_PA1 SILABS_DBUS_EUART0_RTS(0x0, 0x1)
323 #define EUART0_RTS_PA2 SILABS_DBUS_EUART0_RTS(0x0, 0x2)
324 #define EUART0_RTS_PA3 SILABS_DBUS_EUART0_RTS(0x0, 0x3)
325 #define EUART0_RTS_PA4 SILABS_DBUS_EUART0_RTS(0x0, 0x4)
326 #define EUART0_RTS_PA5 SILABS_DBUS_EUART0_RTS(0x0, 0x5)
327 #define EUART0_RTS_PA6 SILABS_DBUS_EUART0_RTS(0x0, 0x6)
328 #define EUART0_RTS_PA7 SILABS_DBUS_EUART0_RTS(0x0, 0x7)
329 #define EUART0_RTS_PA8 SILABS_DBUS_EUART0_RTS(0x0, 0x8)
330 #define EUART0_RTS_PB0 SILABS_DBUS_EUART0_RTS(0x1, 0x0)
331 #define EUART0_RTS_PB1 SILABS_DBUS_EUART0_RTS(0x1, 0x1)
332 #define EUART0_RTS_PB2 SILABS_DBUS_EUART0_RTS(0x1, 0x2)
333 #define EUART0_RTS_PB3 SILABS_DBUS_EUART0_RTS(0x1, 0x3)
334 #define EUART0_RTS_PB4 SILABS_DBUS_EUART0_RTS(0x1, 0x4)
335 #define EUART0_RTS_PC0 SILABS_DBUS_EUART0_RTS(0x2, 0x0)
336 #define EUART0_RTS_PC1 SILABS_DBUS_EUART0_RTS(0x2, 0x1)
337 #define EUART0_RTS_PC2 SILABS_DBUS_EUART0_RTS(0x2, 0x2)
338 #define EUART0_RTS_PC3 SILABS_DBUS_EUART0_RTS(0x2, 0x3)
339 #define EUART0_RTS_PC4 SILABS_DBUS_EUART0_RTS(0x2, 0x4)
340 #define EUART0_RTS_PC5 SILABS_DBUS_EUART0_RTS(0x2, 0x5)
341 #define EUART0_RTS_PC6 SILABS_DBUS_EUART0_RTS(0x2, 0x6)
342 #define EUART0_RTS_PC7 SILABS_DBUS_EUART0_RTS(0x2, 0x7)
343 #define EUART0_RTS_PD0 SILABS_DBUS_EUART0_RTS(0x3, 0x0)
344 #define EUART0_RTS_PD1 SILABS_DBUS_EUART0_RTS(0x3, 0x1)
345 #define EUART0_RTS_PD2 SILABS_DBUS_EUART0_RTS(0x3, 0x2)
346 #define EUART0_RTS_PD3 SILABS_DBUS_EUART0_RTS(0x3, 0x3)
347 #define EUART0_TX_PA0  SILABS_DBUS_EUART0_TX(0x0, 0x0)
348 #define EUART0_TX_PA1  SILABS_DBUS_EUART0_TX(0x0, 0x1)
349 #define EUART0_TX_PA2  SILABS_DBUS_EUART0_TX(0x0, 0x2)
350 #define EUART0_TX_PA3  SILABS_DBUS_EUART0_TX(0x0, 0x3)
351 #define EUART0_TX_PA4  SILABS_DBUS_EUART0_TX(0x0, 0x4)
352 #define EUART0_TX_PA5  SILABS_DBUS_EUART0_TX(0x0, 0x5)
353 #define EUART0_TX_PA6  SILABS_DBUS_EUART0_TX(0x0, 0x6)
354 #define EUART0_TX_PA7  SILABS_DBUS_EUART0_TX(0x0, 0x7)
355 #define EUART0_TX_PA8  SILABS_DBUS_EUART0_TX(0x0, 0x8)
356 #define EUART0_TX_PB0  SILABS_DBUS_EUART0_TX(0x1, 0x0)
357 #define EUART0_TX_PB1  SILABS_DBUS_EUART0_TX(0x1, 0x1)
358 #define EUART0_TX_PB2  SILABS_DBUS_EUART0_TX(0x1, 0x2)
359 #define EUART0_TX_PB3  SILABS_DBUS_EUART0_TX(0x1, 0x3)
360 #define EUART0_TX_PB4  SILABS_DBUS_EUART0_TX(0x1, 0x4)
361 #define EUART0_TX_PC0  SILABS_DBUS_EUART0_TX(0x2, 0x0)
362 #define EUART0_TX_PC1  SILABS_DBUS_EUART0_TX(0x2, 0x1)
363 #define EUART0_TX_PC2  SILABS_DBUS_EUART0_TX(0x2, 0x2)
364 #define EUART0_TX_PC3  SILABS_DBUS_EUART0_TX(0x2, 0x3)
365 #define EUART0_TX_PC4  SILABS_DBUS_EUART0_TX(0x2, 0x4)
366 #define EUART0_TX_PC5  SILABS_DBUS_EUART0_TX(0x2, 0x5)
367 #define EUART0_TX_PC6  SILABS_DBUS_EUART0_TX(0x2, 0x6)
368 #define EUART0_TX_PC7  SILABS_DBUS_EUART0_TX(0x2, 0x7)
369 #define EUART0_TX_PD0  SILABS_DBUS_EUART0_TX(0x3, 0x0)
370 #define EUART0_TX_PD1  SILABS_DBUS_EUART0_TX(0x3, 0x1)
371 #define EUART0_TX_PD2  SILABS_DBUS_EUART0_TX(0x3, 0x2)
372 #define EUART0_TX_PD3  SILABS_DBUS_EUART0_TX(0x3, 0x3)
373 #define EUART0_CTS_PA0 SILABS_DBUS_EUART0_CTS(0x0, 0x0)
374 #define EUART0_CTS_PA1 SILABS_DBUS_EUART0_CTS(0x0, 0x1)
375 #define EUART0_CTS_PA2 SILABS_DBUS_EUART0_CTS(0x0, 0x2)
376 #define EUART0_CTS_PA3 SILABS_DBUS_EUART0_CTS(0x0, 0x3)
377 #define EUART0_CTS_PA4 SILABS_DBUS_EUART0_CTS(0x0, 0x4)
378 #define EUART0_CTS_PA5 SILABS_DBUS_EUART0_CTS(0x0, 0x5)
379 #define EUART0_CTS_PA6 SILABS_DBUS_EUART0_CTS(0x0, 0x6)
380 #define EUART0_CTS_PA7 SILABS_DBUS_EUART0_CTS(0x0, 0x7)
381 #define EUART0_CTS_PA8 SILABS_DBUS_EUART0_CTS(0x0, 0x8)
382 #define EUART0_CTS_PB0 SILABS_DBUS_EUART0_CTS(0x1, 0x0)
383 #define EUART0_CTS_PB1 SILABS_DBUS_EUART0_CTS(0x1, 0x1)
384 #define EUART0_CTS_PB2 SILABS_DBUS_EUART0_CTS(0x1, 0x2)
385 #define EUART0_CTS_PB3 SILABS_DBUS_EUART0_CTS(0x1, 0x3)
386 #define EUART0_CTS_PB4 SILABS_DBUS_EUART0_CTS(0x1, 0x4)
387 #define EUART0_CTS_PC0 SILABS_DBUS_EUART0_CTS(0x2, 0x0)
388 #define EUART0_CTS_PC1 SILABS_DBUS_EUART0_CTS(0x2, 0x1)
389 #define EUART0_CTS_PC2 SILABS_DBUS_EUART0_CTS(0x2, 0x2)
390 #define EUART0_CTS_PC3 SILABS_DBUS_EUART0_CTS(0x2, 0x3)
391 #define EUART0_CTS_PC4 SILABS_DBUS_EUART0_CTS(0x2, 0x4)
392 #define EUART0_CTS_PC5 SILABS_DBUS_EUART0_CTS(0x2, 0x5)
393 #define EUART0_CTS_PC6 SILABS_DBUS_EUART0_CTS(0x2, 0x6)
394 #define EUART0_CTS_PC7 SILABS_DBUS_EUART0_CTS(0x2, 0x7)
395 #define EUART0_CTS_PD0 SILABS_DBUS_EUART0_CTS(0x3, 0x0)
396 #define EUART0_CTS_PD1 SILABS_DBUS_EUART0_CTS(0x3, 0x1)
397 #define EUART0_CTS_PD2 SILABS_DBUS_EUART0_CTS(0x3, 0x2)
398 #define EUART0_CTS_PD3 SILABS_DBUS_EUART0_CTS(0x3, 0x3)
399 #define EUART0_RX_PA0  SILABS_DBUS_EUART0_RX(0x0, 0x0)
400 #define EUART0_RX_PA1  SILABS_DBUS_EUART0_RX(0x0, 0x1)
401 #define EUART0_RX_PA2  SILABS_DBUS_EUART0_RX(0x0, 0x2)
402 #define EUART0_RX_PA3  SILABS_DBUS_EUART0_RX(0x0, 0x3)
403 #define EUART0_RX_PA4  SILABS_DBUS_EUART0_RX(0x0, 0x4)
404 #define EUART0_RX_PA5  SILABS_DBUS_EUART0_RX(0x0, 0x5)
405 #define EUART0_RX_PA6  SILABS_DBUS_EUART0_RX(0x0, 0x6)
406 #define EUART0_RX_PA7  SILABS_DBUS_EUART0_RX(0x0, 0x7)
407 #define EUART0_RX_PA8  SILABS_DBUS_EUART0_RX(0x0, 0x8)
408 #define EUART0_RX_PB0  SILABS_DBUS_EUART0_RX(0x1, 0x0)
409 #define EUART0_RX_PB1  SILABS_DBUS_EUART0_RX(0x1, 0x1)
410 #define EUART0_RX_PB2  SILABS_DBUS_EUART0_RX(0x1, 0x2)
411 #define EUART0_RX_PB3  SILABS_DBUS_EUART0_RX(0x1, 0x3)
412 #define EUART0_RX_PB4  SILABS_DBUS_EUART0_RX(0x1, 0x4)
413 #define EUART0_RX_PC0  SILABS_DBUS_EUART0_RX(0x2, 0x0)
414 #define EUART0_RX_PC1  SILABS_DBUS_EUART0_RX(0x2, 0x1)
415 #define EUART0_RX_PC2  SILABS_DBUS_EUART0_RX(0x2, 0x2)
416 #define EUART0_RX_PC3  SILABS_DBUS_EUART0_RX(0x2, 0x3)
417 #define EUART0_RX_PC4  SILABS_DBUS_EUART0_RX(0x2, 0x4)
418 #define EUART0_RX_PC5  SILABS_DBUS_EUART0_RX(0x2, 0x5)
419 #define EUART0_RX_PC6  SILABS_DBUS_EUART0_RX(0x2, 0x6)
420 #define EUART0_RX_PC7  SILABS_DBUS_EUART0_RX(0x2, 0x7)
421 #define EUART0_RX_PD0  SILABS_DBUS_EUART0_RX(0x3, 0x0)
422 #define EUART0_RX_PD1  SILABS_DBUS_EUART0_RX(0x3, 0x1)
423 #define EUART0_RX_PD2  SILABS_DBUS_EUART0_RX(0x3, 0x2)
424 #define EUART0_RX_PD3  SILABS_DBUS_EUART0_RX(0x3, 0x3)
426 #define MODEM_ANT0_PA0        SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
427 #define MODEM_ANT0_PA1        SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
428 #define MODEM_ANT0_PA2        SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
429 #define MODEM_ANT0_PA3        SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
430 #define MODEM_ANT0_PA4        SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
431 #define MODEM_ANT0_PA5        SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
432 #define MODEM_ANT0_PA6        SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
433 #define MODEM_ANT0_PA7        SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
434 #define MODEM_ANT0_PA8        SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
435 #define MODEM_ANT0_PB0        SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
436 #define MODEM_ANT0_PB1        SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
437 #define MODEM_ANT0_PB2        SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
438 #define MODEM_ANT0_PB3        SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
439 #define MODEM_ANT0_PB4        SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
440 #define MODEM_ANT0_PC0        SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
441 #define MODEM_ANT0_PC1        SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
442 #define MODEM_ANT0_PC2        SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
443 #define MODEM_ANT0_PC3        SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
444 #define MODEM_ANT0_PC4        SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
445 #define MODEM_ANT0_PC5        SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
446 #define MODEM_ANT0_PC6        SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
447 #define MODEM_ANT0_PC7        SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
448 #define MODEM_ANT0_PD0        SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
449 #define MODEM_ANT0_PD1        SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
450 #define MODEM_ANT0_PD2        SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
451 #define MODEM_ANT0_PD3        SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
452 #define MODEM_ANT1_PA0        SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
453 #define MODEM_ANT1_PA1        SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
454 #define MODEM_ANT1_PA2        SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
455 #define MODEM_ANT1_PA3        SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
456 #define MODEM_ANT1_PA4        SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
457 #define MODEM_ANT1_PA5        SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
458 #define MODEM_ANT1_PA6        SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
459 #define MODEM_ANT1_PA7        SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
460 #define MODEM_ANT1_PA8        SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
461 #define MODEM_ANT1_PB0        SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
462 #define MODEM_ANT1_PB1        SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
463 #define MODEM_ANT1_PB2        SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
464 #define MODEM_ANT1_PB3        SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
465 #define MODEM_ANT1_PB4        SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
466 #define MODEM_ANT1_PC0        SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
467 #define MODEM_ANT1_PC1        SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
468 #define MODEM_ANT1_PC2        SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
469 #define MODEM_ANT1_PC3        SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
470 #define MODEM_ANT1_PC4        SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
471 #define MODEM_ANT1_PC5        SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
472 #define MODEM_ANT1_PC6        SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
473 #define MODEM_ANT1_PC7        SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
474 #define MODEM_ANT1_PD0        SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
475 #define MODEM_ANT1_PD1        SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
476 #define MODEM_ANT1_PD2        SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
477 #define MODEM_ANT1_PD3        SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
478 #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
479 #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
480 #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
481 #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
482 #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
483 #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
484 #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
485 #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
486 #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
487 #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
488 #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
489 #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
490 #define MODEM_ANTRR0_PC0      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
491 #define MODEM_ANTRR0_PC1      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
492 #define MODEM_ANTRR0_PC2      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
493 #define MODEM_ANTRR0_PC3      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
494 #define MODEM_ANTRR0_PC4      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
495 #define MODEM_ANTRR0_PC5      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
496 #define MODEM_ANTRR0_PC6      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
497 #define MODEM_ANTRR0_PC7      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
498 #define MODEM_ANTRR0_PD0      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
499 #define MODEM_ANTRR0_PD1      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
500 #define MODEM_ANTRR0_PD2      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
501 #define MODEM_ANTRR0_PD3      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
502 #define MODEM_ANTRR1_PC0      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
503 #define MODEM_ANTRR1_PC1      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
504 #define MODEM_ANTRR1_PC2      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
505 #define MODEM_ANTRR1_PC3      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
506 #define MODEM_ANTRR1_PC4      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
507 #define MODEM_ANTRR1_PC5      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
508 #define MODEM_ANTRR1_PC6      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
509 #define MODEM_ANTRR1_PC7      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
510 #define MODEM_ANTRR1_PD0      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
511 #define MODEM_ANTRR1_PD1      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
512 #define MODEM_ANTRR1_PD2      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
513 #define MODEM_ANTRR1_PD3      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
514 #define MODEM_ANTRR2_PC0      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
515 #define MODEM_ANTRR2_PC1      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
516 #define MODEM_ANTRR2_PC2      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
517 #define MODEM_ANTRR2_PC3      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
518 #define MODEM_ANTRR2_PC4      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
519 #define MODEM_ANTRR2_PC5      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
520 #define MODEM_ANTRR2_PC6      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
521 #define MODEM_ANTRR2_PC7      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
522 #define MODEM_ANTRR2_PD0      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
523 #define MODEM_ANTRR2_PD1      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
524 #define MODEM_ANTRR2_PD2      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
525 #define MODEM_ANTRR2_PD3      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
526 #define MODEM_ANTRR3_PC0      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
527 #define MODEM_ANTRR3_PC1      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
528 #define MODEM_ANTRR3_PC2      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
529 #define MODEM_ANTRR3_PC3      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
530 #define MODEM_ANTRR3_PC4      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
531 #define MODEM_ANTRR3_PC5      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
532 #define MODEM_ANTRR3_PC6      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
533 #define MODEM_ANTRR3_PC7      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
534 #define MODEM_ANTRR3_PD0      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
535 #define MODEM_ANTRR3_PD1      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
536 #define MODEM_ANTRR3_PD2      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
537 #define MODEM_ANTRR3_PD3      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
538 #define MODEM_ANTRR4_PC0      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
539 #define MODEM_ANTRR4_PC1      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
540 #define MODEM_ANTRR4_PC2      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
541 #define MODEM_ANTRR4_PC3      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
542 #define MODEM_ANTRR4_PC4      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
543 #define MODEM_ANTRR4_PC5      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
544 #define MODEM_ANTRR4_PC6      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
545 #define MODEM_ANTRR4_PC7      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
546 #define MODEM_ANTRR4_PD0      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
547 #define MODEM_ANTRR4_PD1      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
548 #define MODEM_ANTRR4_PD2      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
549 #define MODEM_ANTRR4_PD3      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
550 #define MODEM_ANTRR5_PC0      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
551 #define MODEM_ANTRR5_PC1      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
552 #define MODEM_ANTRR5_PC2      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
553 #define MODEM_ANTRR5_PC3      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
554 #define MODEM_ANTRR5_PC4      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
555 #define MODEM_ANTRR5_PC5      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
556 #define MODEM_ANTRR5_PC6      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
557 #define MODEM_ANTRR5_PC7      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
558 #define MODEM_ANTRR5_PD0      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
559 #define MODEM_ANTRR5_PD1      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
560 #define MODEM_ANTRR5_PD2      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
561 #define MODEM_ANTRR5_PD3      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
562 #define MODEM_ANTSWEN_PC0     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
563 #define MODEM_ANTSWEN_PC1     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
564 #define MODEM_ANTSWEN_PC2     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
565 #define MODEM_ANTSWEN_PC3     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
566 #define MODEM_ANTSWEN_PC4     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
567 #define MODEM_ANTSWEN_PC5     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
568 #define MODEM_ANTSWEN_PC6     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
569 #define MODEM_ANTSWEN_PC7     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
570 #define MODEM_ANTSWEN_PD0     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
571 #define MODEM_ANTSWEN_PD1     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
572 #define MODEM_ANTSWEN_PD2     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
573 #define MODEM_ANTSWEN_PD3     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
574 #define MODEM_ANTSWUS_PC0     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
575 #define MODEM_ANTSWUS_PC1     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
576 #define MODEM_ANTSWUS_PC2     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
577 #define MODEM_ANTSWUS_PC3     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
578 #define MODEM_ANTSWUS_PC4     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
579 #define MODEM_ANTSWUS_PC5     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
580 #define MODEM_ANTSWUS_PC6     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
581 #define MODEM_ANTSWUS_PC7     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
582 #define MODEM_ANTSWUS_PD0     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
583 #define MODEM_ANTSWUS_PD1     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
584 #define MODEM_ANTSWUS_PD2     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
585 #define MODEM_ANTSWUS_PD3     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
586 #define MODEM_ANTTRIG_PC0     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
587 #define MODEM_ANTTRIG_PC1     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
588 #define MODEM_ANTTRIG_PC2     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
589 #define MODEM_ANTTRIG_PC3     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
590 #define MODEM_ANTTRIG_PC4     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
591 #define MODEM_ANTTRIG_PC5     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
592 #define MODEM_ANTTRIG_PC6     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
593 #define MODEM_ANTTRIG_PC7     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
594 #define MODEM_ANTTRIG_PD0     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
595 #define MODEM_ANTTRIG_PD1     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
596 #define MODEM_ANTTRIG_PD2     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
597 #define MODEM_ANTTRIG_PD3     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
598 #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
599 #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
600 #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
601 #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
602 #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
603 #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
604 #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
605 #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
606 #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
607 #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
608 #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
609 #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
610 #define MODEM_DCLK_PA0        SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
611 #define MODEM_DCLK_PA1        SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
612 #define MODEM_DCLK_PA2        SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
613 #define MODEM_DCLK_PA3        SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
614 #define MODEM_DCLK_PA4        SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
615 #define MODEM_DCLK_PA5        SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
616 #define MODEM_DCLK_PA6        SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
617 #define MODEM_DCLK_PA7        SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
618 #define MODEM_DCLK_PA8        SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
619 #define MODEM_DCLK_PB0        SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
620 #define MODEM_DCLK_PB1        SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
621 #define MODEM_DCLK_PB2        SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
622 #define MODEM_DCLK_PB3        SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
623 #define MODEM_DCLK_PB4        SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
624 #define MODEM_DOUT_PA0        SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
625 #define MODEM_DOUT_PA1        SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
626 #define MODEM_DOUT_PA2        SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
627 #define MODEM_DOUT_PA3        SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
628 #define MODEM_DOUT_PA4        SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
629 #define MODEM_DOUT_PA5        SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
630 #define MODEM_DOUT_PA6        SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
631 #define MODEM_DOUT_PA7        SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
632 #define MODEM_DOUT_PA8        SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
633 #define MODEM_DOUT_PB0        SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
634 #define MODEM_DOUT_PB1        SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
635 #define MODEM_DOUT_PB2        SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
636 #define MODEM_DOUT_PB3        SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
637 #define MODEM_DOUT_PB4        SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
638 #define MODEM_DIN_PA0         SILABS_DBUS_MODEM_DIN(0x0, 0x0)
639 #define MODEM_DIN_PA1         SILABS_DBUS_MODEM_DIN(0x0, 0x1)
640 #define MODEM_DIN_PA2         SILABS_DBUS_MODEM_DIN(0x0, 0x2)
641 #define MODEM_DIN_PA3         SILABS_DBUS_MODEM_DIN(0x0, 0x3)
642 #define MODEM_DIN_PA4         SILABS_DBUS_MODEM_DIN(0x0, 0x4)
643 #define MODEM_DIN_PA5         SILABS_DBUS_MODEM_DIN(0x0, 0x5)
644 #define MODEM_DIN_PA6         SILABS_DBUS_MODEM_DIN(0x0, 0x6)
645 #define MODEM_DIN_PA7         SILABS_DBUS_MODEM_DIN(0x0, 0x7)
646 #define MODEM_DIN_PA8         SILABS_DBUS_MODEM_DIN(0x0, 0x8)
647 #define MODEM_DIN_PB0         SILABS_DBUS_MODEM_DIN(0x1, 0x0)
648 #define MODEM_DIN_PB1         SILABS_DBUS_MODEM_DIN(0x1, 0x1)
649 #define MODEM_DIN_PB2         SILABS_DBUS_MODEM_DIN(0x1, 0x2)
650 #define MODEM_DIN_PB3         SILABS_DBUS_MODEM_DIN(0x1, 0x3)
651 #define MODEM_DIN_PB4         SILABS_DBUS_MODEM_DIN(0x1, 0x4)
653 #define PDM_CLK_PA0  SILABS_DBUS_PDM_CLK(0x0, 0x0)
654 #define PDM_CLK_PA1  SILABS_DBUS_PDM_CLK(0x0, 0x1)
655 #define PDM_CLK_PA2  SILABS_DBUS_PDM_CLK(0x0, 0x2)
656 #define PDM_CLK_PA3  SILABS_DBUS_PDM_CLK(0x0, 0x3)
657 #define PDM_CLK_PA4  SILABS_DBUS_PDM_CLK(0x0, 0x4)
658 #define PDM_CLK_PA5  SILABS_DBUS_PDM_CLK(0x0, 0x5)
659 #define PDM_CLK_PA6  SILABS_DBUS_PDM_CLK(0x0, 0x6)
660 #define PDM_CLK_PA7  SILABS_DBUS_PDM_CLK(0x0, 0x7)
661 #define PDM_CLK_PA8  SILABS_DBUS_PDM_CLK(0x0, 0x8)
662 #define PDM_CLK_PB0  SILABS_DBUS_PDM_CLK(0x1, 0x0)
663 #define PDM_CLK_PB1  SILABS_DBUS_PDM_CLK(0x1, 0x1)
664 #define PDM_CLK_PB2  SILABS_DBUS_PDM_CLK(0x1, 0x2)
665 #define PDM_CLK_PB3  SILABS_DBUS_PDM_CLK(0x1, 0x3)
666 #define PDM_CLK_PB4  SILABS_DBUS_PDM_CLK(0x1, 0x4)
667 #define PDM_CLK_PC0  SILABS_DBUS_PDM_CLK(0x2, 0x0)
668 #define PDM_CLK_PC1  SILABS_DBUS_PDM_CLK(0x2, 0x1)
669 #define PDM_CLK_PC2  SILABS_DBUS_PDM_CLK(0x2, 0x2)
670 #define PDM_CLK_PC3  SILABS_DBUS_PDM_CLK(0x2, 0x3)
671 #define PDM_CLK_PC4  SILABS_DBUS_PDM_CLK(0x2, 0x4)
672 #define PDM_CLK_PC5  SILABS_DBUS_PDM_CLK(0x2, 0x5)
673 #define PDM_CLK_PC6  SILABS_DBUS_PDM_CLK(0x2, 0x6)
674 #define PDM_CLK_PC7  SILABS_DBUS_PDM_CLK(0x2, 0x7)
675 #define PDM_CLK_PD0  SILABS_DBUS_PDM_CLK(0x3, 0x0)
676 #define PDM_CLK_PD1  SILABS_DBUS_PDM_CLK(0x3, 0x1)
677 #define PDM_CLK_PD2  SILABS_DBUS_PDM_CLK(0x3, 0x2)
678 #define PDM_CLK_PD3  SILABS_DBUS_PDM_CLK(0x3, 0x3)
679 #define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
680 #define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
681 #define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
682 #define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
683 #define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
684 #define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
685 #define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
686 #define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
687 #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
688 #define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
689 #define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
690 #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
691 #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
692 #define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
693 #define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
694 #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
695 #define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
696 #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
697 #define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
698 #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
699 #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
700 #define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
701 #define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
702 #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
703 #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
704 #define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
705 #define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
706 #define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
707 #define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
708 #define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
709 #define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
710 #define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
711 #define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
712 #define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
713 #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
714 #define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
715 #define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
716 #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
717 #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
718 #define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
719 #define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
720 #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
721 #define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
722 #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
723 #define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
724 #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
725 #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
726 #define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
727 #define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
728 #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
729 #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
730 #define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
732 #define PRS0_ASYNCH0_PA0  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
733 #define PRS0_ASYNCH0_PA1  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
734 #define PRS0_ASYNCH0_PA2  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
735 #define PRS0_ASYNCH0_PA3  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
736 #define PRS0_ASYNCH0_PA4  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
737 #define PRS0_ASYNCH0_PA5  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
738 #define PRS0_ASYNCH0_PA6  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
739 #define PRS0_ASYNCH0_PA7  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
740 #define PRS0_ASYNCH0_PA8  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
741 #define PRS0_ASYNCH0_PB0  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
742 #define PRS0_ASYNCH0_PB1  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
743 #define PRS0_ASYNCH0_PB2  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
744 #define PRS0_ASYNCH0_PB3  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
745 #define PRS0_ASYNCH0_PB4  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
746 #define PRS0_ASYNCH1_PA0  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
747 #define PRS0_ASYNCH1_PA1  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
748 #define PRS0_ASYNCH1_PA2  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
749 #define PRS0_ASYNCH1_PA3  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
750 #define PRS0_ASYNCH1_PA4  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
751 #define PRS0_ASYNCH1_PA5  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
752 #define PRS0_ASYNCH1_PA6  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
753 #define PRS0_ASYNCH1_PA7  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
754 #define PRS0_ASYNCH1_PA8  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
755 #define PRS0_ASYNCH1_PB0  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
756 #define PRS0_ASYNCH1_PB1  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
757 #define PRS0_ASYNCH1_PB2  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
758 #define PRS0_ASYNCH1_PB3  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
759 #define PRS0_ASYNCH1_PB4  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
760 #define PRS0_ASYNCH2_PA0  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
761 #define PRS0_ASYNCH2_PA1  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
762 #define PRS0_ASYNCH2_PA2  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
763 #define PRS0_ASYNCH2_PA3  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
764 #define PRS0_ASYNCH2_PA4  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
765 #define PRS0_ASYNCH2_PA5  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
766 #define PRS0_ASYNCH2_PA6  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
767 #define PRS0_ASYNCH2_PA7  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
768 #define PRS0_ASYNCH2_PA8  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
769 #define PRS0_ASYNCH2_PB0  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
770 #define PRS0_ASYNCH2_PB1  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
771 #define PRS0_ASYNCH2_PB2  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
772 #define PRS0_ASYNCH2_PB3  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
773 #define PRS0_ASYNCH2_PB4  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
774 #define PRS0_ASYNCH3_PA0  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
775 #define PRS0_ASYNCH3_PA1  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
776 #define PRS0_ASYNCH3_PA2  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
777 #define PRS0_ASYNCH3_PA3  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
778 #define PRS0_ASYNCH3_PA4  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
779 #define PRS0_ASYNCH3_PA5  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
780 #define PRS0_ASYNCH3_PA6  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
781 #define PRS0_ASYNCH3_PA7  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
782 #define PRS0_ASYNCH3_PA8  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
783 #define PRS0_ASYNCH3_PB0  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
784 #define PRS0_ASYNCH3_PB1  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
785 #define PRS0_ASYNCH3_PB2  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
786 #define PRS0_ASYNCH3_PB3  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
787 #define PRS0_ASYNCH3_PB4  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
788 #define PRS0_ASYNCH4_PA0  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
789 #define PRS0_ASYNCH4_PA1  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
790 #define PRS0_ASYNCH4_PA2  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
791 #define PRS0_ASYNCH4_PA3  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
792 #define PRS0_ASYNCH4_PA4  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
793 #define PRS0_ASYNCH4_PA5  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
794 #define PRS0_ASYNCH4_PA6  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
795 #define PRS0_ASYNCH4_PA7  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
796 #define PRS0_ASYNCH4_PA8  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
797 #define PRS0_ASYNCH4_PB0  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
798 #define PRS0_ASYNCH4_PB1  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
799 #define PRS0_ASYNCH4_PB2  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
800 #define PRS0_ASYNCH4_PB3  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
801 #define PRS0_ASYNCH4_PB4  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
802 #define PRS0_ASYNCH5_PA0  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
803 #define PRS0_ASYNCH5_PA1  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
804 #define PRS0_ASYNCH5_PA2  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
805 #define PRS0_ASYNCH5_PA3  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
806 #define PRS0_ASYNCH5_PA4  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
807 #define PRS0_ASYNCH5_PA5  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
808 #define PRS0_ASYNCH5_PA6  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
809 #define PRS0_ASYNCH5_PA7  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
810 #define PRS0_ASYNCH5_PA8  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
811 #define PRS0_ASYNCH5_PB0  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
812 #define PRS0_ASYNCH5_PB1  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
813 #define PRS0_ASYNCH5_PB2  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
814 #define PRS0_ASYNCH5_PB3  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
815 #define PRS0_ASYNCH5_PB4  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
816 #define PRS0_ASYNCH6_PC0  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
817 #define PRS0_ASYNCH6_PC1  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
818 #define PRS0_ASYNCH6_PC2  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
819 #define PRS0_ASYNCH6_PC3  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
820 #define PRS0_ASYNCH6_PC4  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
821 #define PRS0_ASYNCH6_PC5  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
822 #define PRS0_ASYNCH6_PC6  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
823 #define PRS0_ASYNCH6_PC7  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
824 #define PRS0_ASYNCH6_PD0  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
825 #define PRS0_ASYNCH6_PD1  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
826 #define PRS0_ASYNCH6_PD2  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
827 #define PRS0_ASYNCH6_PD3  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
828 #define PRS0_ASYNCH7_PC0  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
829 #define PRS0_ASYNCH7_PC1  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
830 #define PRS0_ASYNCH7_PC2  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
831 #define PRS0_ASYNCH7_PC3  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
832 #define PRS0_ASYNCH7_PC4  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
833 #define PRS0_ASYNCH7_PC5  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
834 #define PRS0_ASYNCH7_PC6  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
835 #define PRS0_ASYNCH7_PC7  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
836 #define PRS0_ASYNCH7_PD0  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
837 #define PRS0_ASYNCH7_PD1  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
838 #define PRS0_ASYNCH7_PD2  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
839 #define PRS0_ASYNCH7_PD3  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
840 #define PRS0_ASYNCH8_PC0  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
841 #define PRS0_ASYNCH8_PC1  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
842 #define PRS0_ASYNCH8_PC2  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
843 #define PRS0_ASYNCH8_PC3  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
844 #define PRS0_ASYNCH8_PC4  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
845 #define PRS0_ASYNCH8_PC5  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
846 #define PRS0_ASYNCH8_PC6  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
847 #define PRS0_ASYNCH8_PC7  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
848 #define PRS0_ASYNCH8_PD0  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
849 #define PRS0_ASYNCH8_PD1  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
850 #define PRS0_ASYNCH8_PD2  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
851 #define PRS0_ASYNCH8_PD3  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
852 #define PRS0_ASYNCH9_PC0  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
853 #define PRS0_ASYNCH9_PC1  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
854 #define PRS0_ASYNCH9_PC2  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
855 #define PRS0_ASYNCH9_PC3  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
856 #define PRS0_ASYNCH9_PC4  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
857 #define PRS0_ASYNCH9_PC5  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
858 #define PRS0_ASYNCH9_PC6  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
859 #define PRS0_ASYNCH9_PC7  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
860 #define PRS0_ASYNCH9_PD0  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
861 #define PRS0_ASYNCH9_PD1  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
862 #define PRS0_ASYNCH9_PD2  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
863 #define PRS0_ASYNCH9_PD3  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
864 #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
865 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
866 #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
867 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
868 #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
869 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
870 #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
871 #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
872 #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
873 #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
874 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
875 #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
876 #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
877 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
878 #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
879 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
880 #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
881 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
882 #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
883 #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
884 #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
885 #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
886 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
887 #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
888 #define PRS0_SYNCH0_PA0   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
889 #define PRS0_SYNCH0_PA1   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
890 #define PRS0_SYNCH0_PA2   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
891 #define PRS0_SYNCH0_PA3   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
892 #define PRS0_SYNCH0_PA4   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
893 #define PRS0_SYNCH0_PA5   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
894 #define PRS0_SYNCH0_PA6   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
895 #define PRS0_SYNCH0_PA7   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
896 #define PRS0_SYNCH0_PA8   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
897 #define PRS0_SYNCH0_PB0   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
898 #define PRS0_SYNCH0_PB1   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
899 #define PRS0_SYNCH0_PB2   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
900 #define PRS0_SYNCH0_PB3   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
901 #define PRS0_SYNCH0_PB4   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
902 #define PRS0_SYNCH0_PC0   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
903 #define PRS0_SYNCH0_PC1   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
904 #define PRS0_SYNCH0_PC2   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
905 #define PRS0_SYNCH0_PC3   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
906 #define PRS0_SYNCH0_PC4   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
907 #define PRS0_SYNCH0_PC5   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
908 #define PRS0_SYNCH0_PC6   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
909 #define PRS0_SYNCH0_PC7   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
910 #define PRS0_SYNCH0_PD0   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
911 #define PRS0_SYNCH0_PD1   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
912 #define PRS0_SYNCH0_PD2   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
913 #define PRS0_SYNCH0_PD3   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
914 #define PRS0_SYNCH1_PA0   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
915 #define PRS0_SYNCH1_PA1   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
916 #define PRS0_SYNCH1_PA2   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
917 #define PRS0_SYNCH1_PA3   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
918 #define PRS0_SYNCH1_PA4   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
919 #define PRS0_SYNCH1_PA5   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
920 #define PRS0_SYNCH1_PA6   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
921 #define PRS0_SYNCH1_PA7   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
922 #define PRS0_SYNCH1_PA8   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
923 #define PRS0_SYNCH1_PB0   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
924 #define PRS0_SYNCH1_PB1   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
925 #define PRS0_SYNCH1_PB2   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
926 #define PRS0_SYNCH1_PB3   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
927 #define PRS0_SYNCH1_PB4   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
928 #define PRS0_SYNCH1_PC0   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
929 #define PRS0_SYNCH1_PC1   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
930 #define PRS0_SYNCH1_PC2   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
931 #define PRS0_SYNCH1_PC3   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
932 #define PRS0_SYNCH1_PC4   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
933 #define PRS0_SYNCH1_PC5   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
934 #define PRS0_SYNCH1_PC6   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
935 #define PRS0_SYNCH1_PC7   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
936 #define PRS0_SYNCH1_PD0   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
937 #define PRS0_SYNCH1_PD1   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
938 #define PRS0_SYNCH1_PD2   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
939 #define PRS0_SYNCH1_PD3   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
940 #define PRS0_SYNCH2_PA0   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
941 #define PRS0_SYNCH2_PA1   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
942 #define PRS0_SYNCH2_PA2   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
943 #define PRS0_SYNCH2_PA3   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
944 #define PRS0_SYNCH2_PA4   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
945 #define PRS0_SYNCH2_PA5   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
946 #define PRS0_SYNCH2_PA6   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
947 #define PRS0_SYNCH2_PA7   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
948 #define PRS0_SYNCH2_PA8   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
949 #define PRS0_SYNCH2_PB0   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
950 #define PRS0_SYNCH2_PB1   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
951 #define PRS0_SYNCH2_PB2   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
952 #define PRS0_SYNCH2_PB3   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
953 #define PRS0_SYNCH2_PB4   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
954 #define PRS0_SYNCH2_PC0   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
955 #define PRS0_SYNCH2_PC1   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
956 #define PRS0_SYNCH2_PC2   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
957 #define PRS0_SYNCH2_PC3   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
958 #define PRS0_SYNCH2_PC4   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
959 #define PRS0_SYNCH2_PC5   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
960 #define PRS0_SYNCH2_PC6   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
961 #define PRS0_SYNCH2_PC7   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
962 #define PRS0_SYNCH2_PD0   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
963 #define PRS0_SYNCH2_PD1   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
964 #define PRS0_SYNCH2_PD2   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
965 #define PRS0_SYNCH2_PD3   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
966 #define PRS0_SYNCH3_PA0   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
967 #define PRS0_SYNCH3_PA1   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
968 #define PRS0_SYNCH3_PA2   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
969 #define PRS0_SYNCH3_PA3   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
970 #define PRS0_SYNCH3_PA4   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
971 #define PRS0_SYNCH3_PA5   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
972 #define PRS0_SYNCH3_PA6   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
973 #define PRS0_SYNCH3_PA7   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
974 #define PRS0_SYNCH3_PA8   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
975 #define PRS0_SYNCH3_PB0   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
976 #define PRS0_SYNCH3_PB1   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
977 #define PRS0_SYNCH3_PB2   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
978 #define PRS0_SYNCH3_PB3   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
979 #define PRS0_SYNCH3_PB4   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
980 #define PRS0_SYNCH3_PC0   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
981 #define PRS0_SYNCH3_PC1   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
982 #define PRS0_SYNCH3_PC2   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
983 #define PRS0_SYNCH3_PC3   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
984 #define PRS0_SYNCH3_PC4   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
985 #define PRS0_SYNCH3_PC5   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
986 #define PRS0_SYNCH3_PC6   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
987 #define PRS0_SYNCH3_PC7   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
988 #define PRS0_SYNCH3_PD0   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
989 #define PRS0_SYNCH3_PD1   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
990 #define PRS0_SYNCH3_PD2   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
991 #define PRS0_SYNCH3_PD3   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
993 #define TIMER0_CC0_PA0   SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
994 #define TIMER0_CC0_PA1   SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
995 #define TIMER0_CC0_PA2   SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
996 #define TIMER0_CC0_PA3   SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
997 #define TIMER0_CC0_PA4   SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
998 #define TIMER0_CC0_PA5   SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
999 #define TIMER0_CC0_PA6   SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1000 #define TIMER0_CC0_PA7   SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
1001 #define TIMER0_CC0_PA8   SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1002 #define TIMER0_CC0_PB0   SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1003 #define TIMER0_CC0_PB1   SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1004 #define TIMER0_CC0_PB2   SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1005 #define TIMER0_CC0_PB3   SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1006 #define TIMER0_CC0_PB4   SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1007 #define TIMER0_CC0_PC0   SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1008 #define TIMER0_CC0_PC1   SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1009 #define TIMER0_CC0_PC2   SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1010 #define TIMER0_CC0_PC3   SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1011 #define TIMER0_CC0_PC4   SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1012 #define TIMER0_CC0_PC5   SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1013 #define TIMER0_CC0_PC6   SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1014 #define TIMER0_CC0_PC7   SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1015 #define TIMER0_CC0_PD0   SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1016 #define TIMER0_CC0_PD1   SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1017 #define TIMER0_CC0_PD2   SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1018 #define TIMER0_CC0_PD3   SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1019 #define TIMER0_CC1_PA0   SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
1020 #define TIMER0_CC1_PA1   SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1021 #define TIMER0_CC1_PA2   SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1022 #define TIMER0_CC1_PA3   SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1023 #define TIMER0_CC1_PA4   SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
1024 #define TIMER0_CC1_PA5   SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1025 #define TIMER0_CC1_PA6   SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1026 #define TIMER0_CC1_PA7   SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
1027 #define TIMER0_CC1_PA8   SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1028 #define TIMER0_CC1_PB0   SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1029 #define TIMER0_CC1_PB1   SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1030 #define TIMER0_CC1_PB2   SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1031 #define TIMER0_CC1_PB3   SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1032 #define TIMER0_CC1_PB4   SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1033 #define TIMER0_CC1_PC0   SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1034 #define TIMER0_CC1_PC1   SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1035 #define TIMER0_CC1_PC2   SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1036 #define TIMER0_CC1_PC3   SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1037 #define TIMER0_CC1_PC4   SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1038 #define TIMER0_CC1_PC5   SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1039 #define TIMER0_CC1_PC6   SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1040 #define TIMER0_CC1_PC7   SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1041 #define TIMER0_CC1_PD0   SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1042 #define TIMER0_CC1_PD1   SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1043 #define TIMER0_CC1_PD2   SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1044 #define TIMER0_CC1_PD3   SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1045 #define TIMER0_CC2_PA0   SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
1046 #define TIMER0_CC2_PA1   SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1047 #define TIMER0_CC2_PA2   SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1048 #define TIMER0_CC2_PA3   SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1049 #define TIMER0_CC2_PA4   SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
1050 #define TIMER0_CC2_PA5   SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1051 #define TIMER0_CC2_PA6   SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1052 #define TIMER0_CC2_PA7   SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
1053 #define TIMER0_CC2_PA8   SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1054 #define TIMER0_CC2_PB0   SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1055 #define TIMER0_CC2_PB1   SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1056 #define TIMER0_CC2_PB2   SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1057 #define TIMER0_CC2_PB3   SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1058 #define TIMER0_CC2_PB4   SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1059 #define TIMER0_CC2_PC0   SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1060 #define TIMER0_CC2_PC1   SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1061 #define TIMER0_CC2_PC2   SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1062 #define TIMER0_CC2_PC3   SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1063 #define TIMER0_CC2_PC4   SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1064 #define TIMER0_CC2_PC5   SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1065 #define TIMER0_CC2_PC6   SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1066 #define TIMER0_CC2_PC7   SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1067 #define TIMER0_CC2_PD0   SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1068 #define TIMER0_CC2_PD1   SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1069 #define TIMER0_CC2_PD2   SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1070 #define TIMER0_CC2_PD3   SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1071 #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
1072 #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1073 #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1074 #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1075 #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
1076 #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1077 #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1078 #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
1079 #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1080 #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1081 #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1082 #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1083 #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1084 #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1085 #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1086 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1087 #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1088 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1089 #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1090 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1091 #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1092 #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1093 #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1094 #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1095 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1096 #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1097 #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
1098 #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1099 #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1100 #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1101 #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
1102 #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1103 #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1104 #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
1105 #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1106 #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1107 #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1108 #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1109 #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1110 #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1111 #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1112 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1113 #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1114 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1115 #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1116 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1117 #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1118 #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1119 #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1120 #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1121 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1122 #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1123 #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
1124 #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1125 #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1126 #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1127 #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
1128 #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1129 #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
1130 #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
1131 #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1132 #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
1133 #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
1134 #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1135 #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1136 #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
1137 #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
1138 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1139 #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
1140 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1141 #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
1142 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1143 #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1144 #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
1145 #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
1146 #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1147 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1148 #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
1150 #define TIMER1_CC0_PA0   SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
1151 #define TIMER1_CC0_PA1   SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
1152 #define TIMER1_CC0_PA2   SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
1153 #define TIMER1_CC0_PA3   SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
1154 #define TIMER1_CC0_PA4   SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
1155 #define TIMER1_CC0_PA5   SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
1156 #define TIMER1_CC0_PA6   SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
1157 #define TIMER1_CC0_PA7   SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
1158 #define TIMER1_CC0_PA8   SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1159 #define TIMER1_CC0_PB0   SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
1160 #define TIMER1_CC0_PB1   SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
1161 #define TIMER1_CC0_PB2   SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1162 #define TIMER1_CC0_PB3   SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1163 #define TIMER1_CC0_PB4   SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
1164 #define TIMER1_CC0_PC0   SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
1165 #define TIMER1_CC0_PC1   SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1166 #define TIMER1_CC0_PC2   SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
1167 #define TIMER1_CC0_PC3   SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1168 #define TIMER1_CC0_PC4   SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
1169 #define TIMER1_CC0_PC5   SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1170 #define TIMER1_CC0_PC6   SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1171 #define TIMER1_CC0_PC7   SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
1172 #define TIMER1_CC0_PD0   SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
1173 #define TIMER1_CC0_PD1   SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1174 #define TIMER1_CC0_PD2   SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1175 #define TIMER1_CC0_PD3   SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
1176 #define TIMER1_CC1_PA0   SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
1177 #define TIMER1_CC1_PA1   SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
1178 #define TIMER1_CC1_PA2   SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
1179 #define TIMER1_CC1_PA3   SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
1180 #define TIMER1_CC1_PA4   SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
1181 #define TIMER1_CC1_PA5   SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
1182 #define TIMER1_CC1_PA6   SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
1183 #define TIMER1_CC1_PA7   SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
1184 #define TIMER1_CC1_PA8   SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1185 #define TIMER1_CC1_PB0   SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
1186 #define TIMER1_CC1_PB1   SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
1187 #define TIMER1_CC1_PB2   SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1188 #define TIMER1_CC1_PB3   SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1189 #define TIMER1_CC1_PB4   SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
1190 #define TIMER1_CC1_PC0   SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
1191 #define TIMER1_CC1_PC1   SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1192 #define TIMER1_CC1_PC2   SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
1193 #define TIMER1_CC1_PC3   SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1194 #define TIMER1_CC1_PC4   SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
1195 #define TIMER1_CC1_PC5   SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1196 #define TIMER1_CC1_PC6   SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1197 #define TIMER1_CC1_PC7   SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
1198 #define TIMER1_CC1_PD0   SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
1199 #define TIMER1_CC1_PD1   SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1200 #define TIMER1_CC1_PD2   SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1201 #define TIMER1_CC1_PD3   SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
1202 #define TIMER1_CC2_PA0   SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
1203 #define TIMER1_CC2_PA1   SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
1204 #define TIMER1_CC2_PA2   SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
1205 #define TIMER1_CC2_PA3   SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
1206 #define TIMER1_CC2_PA4   SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
1207 #define TIMER1_CC2_PA5   SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
1208 #define TIMER1_CC2_PA6   SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
1209 #define TIMER1_CC2_PA7   SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
1210 #define TIMER1_CC2_PA8   SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1211 #define TIMER1_CC2_PB0   SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
1212 #define TIMER1_CC2_PB1   SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
1213 #define TIMER1_CC2_PB2   SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1214 #define TIMER1_CC2_PB3   SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1215 #define TIMER1_CC2_PB4   SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
1216 #define TIMER1_CC2_PC0   SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
1217 #define TIMER1_CC2_PC1   SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1218 #define TIMER1_CC2_PC2   SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
1219 #define TIMER1_CC2_PC3   SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1220 #define TIMER1_CC2_PC4   SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
1221 #define TIMER1_CC2_PC5   SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1222 #define TIMER1_CC2_PC6   SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1223 #define TIMER1_CC2_PC7   SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
1224 #define TIMER1_CC2_PD0   SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
1225 #define TIMER1_CC2_PD1   SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1226 #define TIMER1_CC2_PD2   SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1227 #define TIMER1_CC2_PD3   SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
1228 #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
1229 #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
1230 #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
1231 #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
1232 #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
1233 #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
1234 #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
1235 #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
1236 #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1237 #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
1238 #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
1239 #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1240 #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1241 #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
1242 #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
1243 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1244 #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
1245 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1246 #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
1247 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1248 #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1249 #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
1250 #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
1251 #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1252 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1253 #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
1254 #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
1255 #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
1256 #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
1257 #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
1258 #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
1259 #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
1260 #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
1261 #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
1262 #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1263 #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
1264 #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
1265 #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1266 #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1267 #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
1268 #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
1269 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1270 #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
1271 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1272 #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
1273 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1274 #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1275 #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
1276 #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
1277 #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1278 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1279 #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
1280 #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
1281 #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
1282 #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
1283 #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
1284 #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
1285 #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
1286 #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
1287 #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
1288 #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1289 #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
1290 #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
1291 #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1292 #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1293 #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
1294 #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
1295 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1296 #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
1297 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1298 #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
1299 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1300 #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1301 #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
1302 #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
1303 #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1304 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1305 #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
1307 #define TIMER2_CC0_PA0   SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
1308 #define TIMER2_CC0_PA1   SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
1309 #define TIMER2_CC0_PA2   SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
1310 #define TIMER2_CC0_PA3   SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
1311 #define TIMER2_CC0_PA4   SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
1312 #define TIMER2_CC0_PA5   SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
1313 #define TIMER2_CC0_PA6   SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
1314 #define TIMER2_CC0_PA7   SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
1315 #define TIMER2_CC0_PA8   SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1316 #define TIMER2_CC0_PB0   SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
1317 #define TIMER2_CC0_PB1   SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
1318 #define TIMER2_CC0_PB2   SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1319 #define TIMER2_CC0_PB3   SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1320 #define TIMER2_CC0_PB4   SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
1321 #define TIMER2_CC1_PA0   SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
1322 #define TIMER2_CC1_PA1   SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
1323 #define TIMER2_CC1_PA2   SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
1324 #define TIMER2_CC1_PA3   SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
1325 #define TIMER2_CC1_PA4   SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
1326 #define TIMER2_CC1_PA5   SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
1327 #define TIMER2_CC1_PA6   SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
1328 #define TIMER2_CC1_PA7   SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
1329 #define TIMER2_CC1_PA8   SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1330 #define TIMER2_CC1_PB0   SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
1331 #define TIMER2_CC1_PB1   SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
1332 #define TIMER2_CC1_PB2   SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1333 #define TIMER2_CC1_PB3   SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1334 #define TIMER2_CC1_PB4   SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
1335 #define TIMER2_CC2_PA0   SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
1336 #define TIMER2_CC2_PA1   SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
1337 #define TIMER2_CC2_PA2   SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
1338 #define TIMER2_CC2_PA3   SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
1339 #define TIMER2_CC2_PA4   SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
1340 #define TIMER2_CC2_PA5   SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
1341 #define TIMER2_CC2_PA6   SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
1342 #define TIMER2_CC2_PA7   SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
1343 #define TIMER2_CC2_PA8   SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1344 #define TIMER2_CC2_PB0   SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
1345 #define TIMER2_CC2_PB1   SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
1346 #define TIMER2_CC2_PB2   SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1347 #define TIMER2_CC2_PB3   SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1348 #define TIMER2_CC2_PB4   SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
1349 #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
1350 #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
1351 #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
1352 #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
1353 #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
1354 #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
1355 #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
1356 #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
1357 #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1358 #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
1359 #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
1360 #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1361 #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1362 #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
1363 #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
1364 #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
1365 #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
1366 #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
1367 #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
1368 #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
1369 #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
1370 #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
1371 #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1372 #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
1373 #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
1374 #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1375 #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1376 #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
1377 #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
1378 #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
1379 #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
1380 #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
1381 #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
1382 #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
1383 #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
1384 #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
1385 #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1386 #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
1387 #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
1388 #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1389 #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1390 #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
1392 #define TIMER3_CC0_PC0   SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
1393 #define TIMER3_CC0_PC1   SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1394 #define TIMER3_CC0_PC2   SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
1395 #define TIMER3_CC0_PC3   SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1396 #define TIMER3_CC0_PC4   SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
1397 #define TIMER3_CC0_PC5   SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1398 #define TIMER3_CC0_PC6   SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1399 #define TIMER3_CC0_PC7   SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
1400 #define TIMER3_CC0_PD0   SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
1401 #define TIMER3_CC0_PD1   SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1402 #define TIMER3_CC0_PD2   SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1403 #define TIMER3_CC0_PD3   SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
1404 #define TIMER3_CC1_PC0   SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
1405 #define TIMER3_CC1_PC1   SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1406 #define TIMER3_CC1_PC2   SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
1407 #define TIMER3_CC1_PC3   SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1408 #define TIMER3_CC1_PC4   SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
1409 #define TIMER3_CC1_PC5   SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1410 #define TIMER3_CC1_PC6   SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1411 #define TIMER3_CC1_PC7   SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
1412 #define TIMER3_CC1_PD0   SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
1413 #define TIMER3_CC1_PD1   SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1414 #define TIMER3_CC1_PD2   SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1415 #define TIMER3_CC1_PD3   SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
1416 #define TIMER3_CC2_PC0   SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
1417 #define TIMER3_CC2_PC1   SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1418 #define TIMER3_CC2_PC2   SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
1419 #define TIMER3_CC2_PC3   SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1420 #define TIMER3_CC2_PC4   SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
1421 #define TIMER3_CC2_PC5   SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1422 #define TIMER3_CC2_PC6   SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1423 #define TIMER3_CC2_PC7   SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
1424 #define TIMER3_CC2_PD0   SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
1425 #define TIMER3_CC2_PD1   SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1426 #define TIMER3_CC2_PD2   SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1427 #define TIMER3_CC2_PD3   SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
1428 #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
1429 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1430 #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
1431 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1432 #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
1433 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1434 #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1435 #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
1436 #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
1437 #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1438 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1439 #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
1440 #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
1441 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1442 #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
1443 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1444 #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
1445 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1446 #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1447 #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
1448 #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
1449 #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1450 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1451 #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
1452 #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
1453 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1454 #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
1455 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1456 #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
1457 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1458 #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1459 #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
1460 #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
1461 #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1462 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1463 #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
1465 #define TIMER4_CC0_PA0   SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
1466 #define TIMER4_CC0_PA1   SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
1467 #define TIMER4_CC0_PA2   SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
1468 #define TIMER4_CC0_PA3   SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
1469 #define TIMER4_CC0_PA4   SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
1470 #define TIMER4_CC0_PA5   SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
1471 #define TIMER4_CC0_PA6   SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
1472 #define TIMER4_CC0_PA7   SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
1473 #define TIMER4_CC0_PA8   SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1474 #define TIMER4_CC0_PB0   SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
1475 #define TIMER4_CC0_PB1   SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
1476 #define TIMER4_CC0_PB2   SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1477 #define TIMER4_CC0_PB3   SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1478 #define TIMER4_CC0_PB4   SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
1479 #define TIMER4_CC1_PA0   SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
1480 #define TIMER4_CC1_PA1   SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
1481 #define TIMER4_CC1_PA2   SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
1482 #define TIMER4_CC1_PA3   SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
1483 #define TIMER4_CC1_PA4   SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
1484 #define TIMER4_CC1_PA5   SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
1485 #define TIMER4_CC1_PA6   SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
1486 #define TIMER4_CC1_PA7   SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
1487 #define TIMER4_CC1_PA8   SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1488 #define TIMER4_CC1_PB0   SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
1489 #define TIMER4_CC1_PB1   SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
1490 #define TIMER4_CC1_PB2   SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1491 #define TIMER4_CC1_PB3   SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1492 #define TIMER4_CC1_PB4   SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
1493 #define TIMER4_CC2_PA0   SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
1494 #define TIMER4_CC2_PA1   SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
1495 #define TIMER4_CC2_PA2   SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
1496 #define TIMER4_CC2_PA3   SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
1497 #define TIMER4_CC2_PA4   SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
1498 #define TIMER4_CC2_PA5   SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
1499 #define TIMER4_CC2_PA6   SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
1500 #define TIMER4_CC2_PA7   SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
1501 #define TIMER4_CC2_PA8   SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1502 #define TIMER4_CC2_PB0   SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
1503 #define TIMER4_CC2_PB1   SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
1504 #define TIMER4_CC2_PB2   SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1505 #define TIMER4_CC2_PB3   SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1506 #define TIMER4_CC2_PB4   SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
1507 #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
1508 #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
1509 #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
1510 #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
1511 #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
1512 #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
1513 #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
1514 #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
1515 #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1516 #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
1517 #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
1518 #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1519 #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1520 #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
1521 #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
1522 #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
1523 #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
1524 #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
1525 #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
1526 #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
1527 #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
1528 #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
1529 #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1530 #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
1531 #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
1532 #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1533 #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1534 #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
1535 #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
1536 #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
1537 #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
1538 #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
1539 #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
1540 #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
1541 #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
1542 #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
1543 #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1544 #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
1545 #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
1546 #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1547 #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1548 #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
1550 #define USART0_CS_PA0  SILABS_DBUS_USART0_CS(0x0, 0x0)
1551 #define USART0_CS_PA1  SILABS_DBUS_USART0_CS(0x0, 0x1)
1552 #define USART0_CS_PA2  SILABS_DBUS_USART0_CS(0x0, 0x2)
1553 #define USART0_CS_PA3  SILABS_DBUS_USART0_CS(0x0, 0x3)
1554 #define USART0_CS_PA4  SILABS_DBUS_USART0_CS(0x0, 0x4)
1555 #define USART0_CS_PA5  SILABS_DBUS_USART0_CS(0x0, 0x5)
1556 #define USART0_CS_PA6  SILABS_DBUS_USART0_CS(0x0, 0x6)
1557 #define USART0_CS_PA7  SILABS_DBUS_USART0_CS(0x0, 0x7)
1558 #define USART0_CS_PA8  SILABS_DBUS_USART0_CS(0x0, 0x8)
1559 #define USART0_CS_PB0  SILABS_DBUS_USART0_CS(0x1, 0x0)
1560 #define USART0_CS_PB1  SILABS_DBUS_USART0_CS(0x1, 0x1)
1561 #define USART0_CS_PB2  SILABS_DBUS_USART0_CS(0x1, 0x2)
1562 #define USART0_CS_PB3  SILABS_DBUS_USART0_CS(0x1, 0x3)
1563 #define USART0_CS_PB4  SILABS_DBUS_USART0_CS(0x1, 0x4)
1564 #define USART0_CS_PC0  SILABS_DBUS_USART0_CS(0x2, 0x0)
1565 #define USART0_CS_PC1  SILABS_DBUS_USART0_CS(0x2, 0x1)
1566 #define USART0_CS_PC2  SILABS_DBUS_USART0_CS(0x2, 0x2)
1567 #define USART0_CS_PC3  SILABS_DBUS_USART0_CS(0x2, 0x3)
1568 #define USART0_CS_PC4  SILABS_DBUS_USART0_CS(0x2, 0x4)
1569 #define USART0_CS_PC5  SILABS_DBUS_USART0_CS(0x2, 0x5)
1570 #define USART0_CS_PC6  SILABS_DBUS_USART0_CS(0x2, 0x6)
1571 #define USART0_CS_PC7  SILABS_DBUS_USART0_CS(0x2, 0x7)
1572 #define USART0_CS_PD0  SILABS_DBUS_USART0_CS(0x3, 0x0)
1573 #define USART0_CS_PD1  SILABS_DBUS_USART0_CS(0x3, 0x1)
1574 #define USART0_CS_PD2  SILABS_DBUS_USART0_CS(0x3, 0x2)
1575 #define USART0_CS_PD3  SILABS_DBUS_USART0_CS(0x3, 0x3)
1576 #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
1577 #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
1578 #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
1579 #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
1580 #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
1581 #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
1582 #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
1583 #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
1584 #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1585 #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
1586 #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
1587 #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1588 #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1589 #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
1590 #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
1591 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1592 #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
1593 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1594 #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
1595 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1596 #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1597 #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
1598 #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
1599 #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1600 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1601 #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
1602 #define USART0_RX_PA0  SILABS_DBUS_USART0_RX(0x0, 0x0)
1603 #define USART0_RX_PA1  SILABS_DBUS_USART0_RX(0x0, 0x1)
1604 #define USART0_RX_PA2  SILABS_DBUS_USART0_RX(0x0, 0x2)
1605 #define USART0_RX_PA3  SILABS_DBUS_USART0_RX(0x0, 0x3)
1606 #define USART0_RX_PA4  SILABS_DBUS_USART0_RX(0x0, 0x4)
1607 #define USART0_RX_PA5  SILABS_DBUS_USART0_RX(0x0, 0x5)
1608 #define USART0_RX_PA6  SILABS_DBUS_USART0_RX(0x0, 0x6)
1609 #define USART0_RX_PA7  SILABS_DBUS_USART0_RX(0x0, 0x7)
1610 #define USART0_RX_PA8  SILABS_DBUS_USART0_RX(0x0, 0x8)
1611 #define USART0_RX_PB0  SILABS_DBUS_USART0_RX(0x1, 0x0)
1612 #define USART0_RX_PB1  SILABS_DBUS_USART0_RX(0x1, 0x1)
1613 #define USART0_RX_PB2  SILABS_DBUS_USART0_RX(0x1, 0x2)
1614 #define USART0_RX_PB3  SILABS_DBUS_USART0_RX(0x1, 0x3)
1615 #define USART0_RX_PB4  SILABS_DBUS_USART0_RX(0x1, 0x4)
1616 #define USART0_RX_PC0  SILABS_DBUS_USART0_RX(0x2, 0x0)
1617 #define USART0_RX_PC1  SILABS_DBUS_USART0_RX(0x2, 0x1)
1618 #define USART0_RX_PC2  SILABS_DBUS_USART0_RX(0x2, 0x2)
1619 #define USART0_RX_PC3  SILABS_DBUS_USART0_RX(0x2, 0x3)
1620 #define USART0_RX_PC4  SILABS_DBUS_USART0_RX(0x2, 0x4)
1621 #define USART0_RX_PC5  SILABS_DBUS_USART0_RX(0x2, 0x5)
1622 #define USART0_RX_PC6  SILABS_DBUS_USART0_RX(0x2, 0x6)
1623 #define USART0_RX_PC7  SILABS_DBUS_USART0_RX(0x2, 0x7)
1624 #define USART0_RX_PD0  SILABS_DBUS_USART0_RX(0x3, 0x0)
1625 #define USART0_RX_PD1  SILABS_DBUS_USART0_RX(0x3, 0x1)
1626 #define USART0_RX_PD2  SILABS_DBUS_USART0_RX(0x3, 0x2)
1627 #define USART0_RX_PD3  SILABS_DBUS_USART0_RX(0x3, 0x3)
1628 #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
1629 #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1630 #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1631 #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1632 #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
1633 #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1634 #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1635 #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
1636 #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1637 #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1638 #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1639 #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1640 #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1641 #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
1642 #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1643 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1644 #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1645 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1646 #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1647 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1648 #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1649 #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
1650 #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1651 #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1652 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1653 #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1654 #define USART0_TX_PA0  SILABS_DBUS_USART0_TX(0x0, 0x0)
1655 #define USART0_TX_PA1  SILABS_DBUS_USART0_TX(0x0, 0x1)
1656 #define USART0_TX_PA2  SILABS_DBUS_USART0_TX(0x0, 0x2)
1657 #define USART0_TX_PA3  SILABS_DBUS_USART0_TX(0x0, 0x3)
1658 #define USART0_TX_PA4  SILABS_DBUS_USART0_TX(0x0, 0x4)
1659 #define USART0_TX_PA5  SILABS_DBUS_USART0_TX(0x0, 0x5)
1660 #define USART0_TX_PA6  SILABS_DBUS_USART0_TX(0x0, 0x6)
1661 #define USART0_TX_PA7  SILABS_DBUS_USART0_TX(0x0, 0x7)
1662 #define USART0_TX_PA8  SILABS_DBUS_USART0_TX(0x0, 0x8)
1663 #define USART0_TX_PB0  SILABS_DBUS_USART0_TX(0x1, 0x0)
1664 #define USART0_TX_PB1  SILABS_DBUS_USART0_TX(0x1, 0x1)
1665 #define USART0_TX_PB2  SILABS_DBUS_USART0_TX(0x1, 0x2)
1666 #define USART0_TX_PB3  SILABS_DBUS_USART0_TX(0x1, 0x3)
1667 #define USART0_TX_PB4  SILABS_DBUS_USART0_TX(0x1, 0x4)
1668 #define USART0_TX_PC0  SILABS_DBUS_USART0_TX(0x2, 0x0)
1669 #define USART0_TX_PC1  SILABS_DBUS_USART0_TX(0x2, 0x1)
1670 #define USART0_TX_PC2  SILABS_DBUS_USART0_TX(0x2, 0x2)
1671 #define USART0_TX_PC3  SILABS_DBUS_USART0_TX(0x2, 0x3)
1672 #define USART0_TX_PC4  SILABS_DBUS_USART0_TX(0x2, 0x4)
1673 #define USART0_TX_PC5  SILABS_DBUS_USART0_TX(0x2, 0x5)
1674 #define USART0_TX_PC6  SILABS_DBUS_USART0_TX(0x2, 0x6)
1675 #define USART0_TX_PC7  SILABS_DBUS_USART0_TX(0x2, 0x7)
1676 #define USART0_TX_PD0  SILABS_DBUS_USART0_TX(0x3, 0x0)
1677 #define USART0_TX_PD1  SILABS_DBUS_USART0_TX(0x3, 0x1)
1678 #define USART0_TX_PD2  SILABS_DBUS_USART0_TX(0x3, 0x2)
1679 #define USART0_TX_PD3  SILABS_DBUS_USART0_TX(0x3, 0x3)
1680 #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
1681 #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1682 #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1683 #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1684 #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
1685 #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1686 #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1687 #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
1688 #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1689 #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1690 #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1691 #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1692 #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1693 #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
1694 #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1695 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1696 #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1697 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1698 #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1699 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1700 #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1701 #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
1702 #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1703 #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1704 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1705 #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1707 #define USART1_CS_PA0  SILABS_DBUS_USART1_CS(0x0, 0x0)
1708 #define USART1_CS_PA1  SILABS_DBUS_USART1_CS(0x0, 0x1)
1709 #define USART1_CS_PA2  SILABS_DBUS_USART1_CS(0x0, 0x2)
1710 #define USART1_CS_PA3  SILABS_DBUS_USART1_CS(0x0, 0x3)
1711 #define USART1_CS_PA4  SILABS_DBUS_USART1_CS(0x0, 0x4)
1712 #define USART1_CS_PA5  SILABS_DBUS_USART1_CS(0x0, 0x5)
1713 #define USART1_CS_PA6  SILABS_DBUS_USART1_CS(0x0, 0x6)
1714 #define USART1_CS_PA7  SILABS_DBUS_USART1_CS(0x0, 0x7)
1715 #define USART1_CS_PA8  SILABS_DBUS_USART1_CS(0x0, 0x8)
1716 #define USART1_CS_PB0  SILABS_DBUS_USART1_CS(0x1, 0x0)
1717 #define USART1_CS_PB1  SILABS_DBUS_USART1_CS(0x1, 0x1)
1718 #define USART1_CS_PB2  SILABS_DBUS_USART1_CS(0x1, 0x2)
1719 #define USART1_CS_PB3  SILABS_DBUS_USART1_CS(0x1, 0x3)
1720 #define USART1_CS_PB4  SILABS_DBUS_USART1_CS(0x1, 0x4)
1721 #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
1722 #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1723 #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1724 #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1725 #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
1726 #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1727 #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1728 #define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
1729 #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1730 #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1731 #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1732 #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1733 #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1734 #define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
1735 #define USART1_RX_PA0  SILABS_DBUS_USART1_RX(0x0, 0x0)
1736 #define USART1_RX_PA1  SILABS_DBUS_USART1_RX(0x0, 0x1)
1737 #define USART1_RX_PA2  SILABS_DBUS_USART1_RX(0x0, 0x2)
1738 #define USART1_RX_PA3  SILABS_DBUS_USART1_RX(0x0, 0x3)
1739 #define USART1_RX_PA4  SILABS_DBUS_USART1_RX(0x0, 0x4)
1740 #define USART1_RX_PA5  SILABS_DBUS_USART1_RX(0x0, 0x5)
1741 #define USART1_RX_PA6  SILABS_DBUS_USART1_RX(0x0, 0x6)
1742 #define USART1_RX_PA7  SILABS_DBUS_USART1_RX(0x0, 0x7)
1743 #define USART1_RX_PA8  SILABS_DBUS_USART1_RX(0x0, 0x8)
1744 #define USART1_RX_PB0  SILABS_DBUS_USART1_RX(0x1, 0x0)
1745 #define USART1_RX_PB1  SILABS_DBUS_USART1_RX(0x1, 0x1)
1746 #define USART1_RX_PB2  SILABS_DBUS_USART1_RX(0x1, 0x2)
1747 #define USART1_RX_PB3  SILABS_DBUS_USART1_RX(0x1, 0x3)
1748 #define USART1_RX_PB4  SILABS_DBUS_USART1_RX(0x1, 0x4)
1749 #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
1750 #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
1751 #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
1752 #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
1753 #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
1754 #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
1755 #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
1756 #define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
1757 #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
1758 #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
1759 #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
1760 #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
1761 #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
1762 #define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
1763 #define USART1_TX_PA0  SILABS_DBUS_USART1_TX(0x0, 0x0)
1764 #define USART1_TX_PA1  SILABS_DBUS_USART1_TX(0x0, 0x1)
1765 #define USART1_TX_PA2  SILABS_DBUS_USART1_TX(0x0, 0x2)
1766 #define USART1_TX_PA3  SILABS_DBUS_USART1_TX(0x0, 0x3)
1767 #define USART1_TX_PA4  SILABS_DBUS_USART1_TX(0x0, 0x4)
1768 #define USART1_TX_PA5  SILABS_DBUS_USART1_TX(0x0, 0x5)
1769 #define USART1_TX_PA6  SILABS_DBUS_USART1_TX(0x0, 0x6)
1770 #define USART1_TX_PA7  SILABS_DBUS_USART1_TX(0x0, 0x7)
1771 #define USART1_TX_PA8  SILABS_DBUS_USART1_TX(0x0, 0x8)
1772 #define USART1_TX_PB0  SILABS_DBUS_USART1_TX(0x1, 0x0)
1773 #define USART1_TX_PB1  SILABS_DBUS_USART1_TX(0x1, 0x1)
1774 #define USART1_TX_PB2  SILABS_DBUS_USART1_TX(0x1, 0x2)
1775 #define USART1_TX_PB3  SILABS_DBUS_USART1_TX(0x1, 0x3)
1776 #define USART1_TX_PB4  SILABS_DBUS_USART1_TX(0x1, 0x4)
1777 #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
1778 #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
1779 #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
1780 #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
1781 #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
1782 #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
1783 #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
1784 #define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
1785 #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
1786 #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
1787 #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
1788 #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
1789 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
1790 #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)