Lines Matching full:x6
116 #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
137 #define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6)
180 #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
235 #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
255 #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
299 #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
308 #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
318 #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
338 #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
358 #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
367 #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
376 #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
386 #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
395 #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
404 #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
413 #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
422 #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
431 #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
506 #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
526 #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
546 #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
566 #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
587 #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
607 #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
627 #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
647 #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
667 #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
687 #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
708 #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
728 #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
748 #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
768 #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
788 #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
808 #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
829 #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
838 #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
847 #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
856 #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
865 #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
874 #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
951 #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
971 #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
991 #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
1011 #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1031 #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
1051 #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1072 #define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6)
1081 #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1090 #define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6)
1099 #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
1108 #define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6)
1117 #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)