Lines Matching full:level

10 #define WIFI_MAC_INTR_SOURCE                  0 /* interrupt of WiFi MAC, level*/
13 #define WIFI_BB_INTR_SOURCE                   3 /* interrupt of WiFi BB, level*/
15 #define BT_BB_INTR_SOURCE                     5 /* interrupt of BT BB, level*/
17 #define RWBT_INTR_SOURCE                      7 /* interrupt of RWBT, level*/
18 #define RWBLE_INTR_SOURCE                     8 /* interrupt of RWBLE, level*/
21 #define I2C_MASTER_SOURCE                     11 /* interrupt of I2C Master, level*/
22 #define SLC0_INTR_SOURCE                      12 /* interrupt of SLC0, level*/
23 #define SLC1_INTR_SOURCE                      13 /* interrupt of SLC1, level*/
24 #define UHCI0_INTR_SOURCE                     14 /* interrupt of UHCI0, level*/
25 #define UHCI1_INTR_SOURCE                     15 /* interrupt of UHCI1, level*/
26 #define GPIO_INTR_SOURCE                      16 /* interrupt of GPIO, level*/
28 #define GPIO_INTR_SOURCE2                     18 /* interrupt of GPIO, level*/
30 #define SPI1_INTR_SOURCE                      20 /* interrupt of SPI1, level*/
31 #define SPI2_INTR_SOURCE                      21 /* interrupt of SPI2, level*/
32 #define SPI3_INTR_SOURCE                      22 /* interrupt of SPI3, level*/
33 #define LCD_CAM_INTR_SOURCE                   24 /* interrupt of LCD camera, level*/
34 #define I2S0_INTR_SOURCE                      25 /* interrupt of I2S0, level*/
35 #define I2S1_INTR_SOURCE                      26 /* interrupt of I2S1, level*/
36 #define UART0_INTR_SOURCE                     27 /* interrupt of UART0, level*/
37 #define UART1_INTR_SOURCE                     28 /* interrupt of UART1, level*/
38 #define UART2_INTR_SOURCE                     29 /* interrupt of UART2, level*/
39 #define SDIO_HOST_INTR_SOURCE                 30 /* interrupt of SD/SDIO/MMC HOST, level*/
40 #define PWM0_INTR_SOURCE                      31 /* interrupt of PWM0, level, Reserved*/
41 #define PWM1_INTR_SOURCE                      32 /* interrupt of PWM1, level, Reserved*/
42 #define LEDC_INTR_SOURCE                      35 /* interrupt of LED PWM, level*/
43 #define EFUSE_INTR_SOURCE                     36 /* interrupt of efuse, level, not likely to use*/
44 #define TWAI_INTR_SOURCE                      37 /* interrupt of can, level*/
45 #define USB_INTR_SOURCE                       38 /* interrupt of USB, level*/
46 #define RTC_CORE_INTR_SOURCE                  39 /* interrupt of rtc core and watchdog, level*/
47 #define RMT_INTR_SOURCE                       40 /* interrupt of remote controller, level*/
48 #define PCNT_INTR_SOURCE                      41 /* interrupt of pulse count, level*/
49 #define I2C_EXT0_INTR_SOURCE                  42 /* interrupt of I2C controller1, level*/
50 #define I2C_EXT1_INTR_SOURCE                  43 /* interrupt of I2C controller0, level*/
51 #define SPI2_DMA_INTR_SOURCE                  44 /* interrupt of SPI2 DMA, level*/
52 #define SPI3_DMA_INTR_SOURCE                  45 /* interrupt of SPI3 DMA, level*/
62 #define CACHE_IA_INTR_SOURCE                  56 /* interrupt of Cache Invalid Access, LEVEL*/
66 #define SPI_MEM_REJECT_CACHE_INTR_SOURCE      60 /* interrupt of SPI0/SPI1 Cache/Rejected, LEVEL*/
67 #define DCACHE_PRELOAD0_INTR_SOURCE           61 /* interrupt of DCache preload operation, LEVEL*/
68 #define ICACHE_PRELOAD0_INTR_SOURCE           62 /* interrupt of ICache perload operation, LEVEL*/
69 #define DCACHE_SYNC0_INTR_SOURCE              63 /* interrupt of data cache sync done, LEVEL*/
70 #define ICACHE_SYNC0_INTR_SOURCE              64 /* interrupt of instr. cache sync done, LEVEL*/
71 #define APB_ADC_INTR_SOURCE                   65 /* interrupt of APB ADC, LEVEL*/
72 #define DMA_IN_CH0_INTR_SOURCE                66 /* interrupt of general DMA RX channel 0, LEVEL*/
73 #define DMA_IN_CH1_INTR_SOURCE                67 /* interrupt of general DMA RX channel 1, LEVEL*/
74 #define DMA_IN_CH2_INTR_SOURCE                68 /* interrupt of general DMA RX channel 2, LEVEL*/
75 #define DMA_IN_CH3_INTR_SOURCE                69 /* interrupt of general DMA RX channel 3, LEVEL*/
76 #define DMA_IN_CH4_INTR_SOURCE                70 /* interrupt of general DMA RX channel 4, LEVEL*/
77 #define DMA_OUT_CH0_INTR_SOURCE               71 /* interrupt of general DMA TX channel 0, LEVEL*/
78 #define DMA_OUT_CH1_INTR_SOURCE               72 /* interrupt of general DMA TX channel 1, LEVEL*/
79 #define DMA_OUT_CH2_INTR_SOURCE               73 /* interrupt of general DMA TX channel 2, LEVEL*/
80 #define DMA_OUT_CH3_INTR_SOURCE               74 /* interrupt of general DMA TX channel 3, LEVEL*/
81 #define DMA_OUT_CH4_INTR_SOURCE               75 /* interrupt of general DMA TX channel 4, LEVEL*/
82 #define RSA_INTR_SOURCE                       76 /* interrupt of RSA accelerator, level*/
83 #define AES_INTR_SOURCE                       77 /* interrupt of AES accelerator, level*/
84 #define SHA_INTR_SOURCE                       78 /* interrupt of SHA accelerator, level*/
85 #define FROM_CPU_INTR0_SOURCE                 79 /* interrupt0 generated from a CPU, level*/
86 #define FROM_CPU_INTR1_SOURCE                 80 /* interrupt1 generated from a CPU, level*/
87 #define FROM_CPU_INTR2_SOURCE                 81 /* interrupt2 generated from a CPU, level*/
88 #define FROM_CPU_INTR3_SOURCE                 82 /* interrupt3 generated from a CPU, level*/
89 #define ASSIST_DEBUG_INTR_SOURCE              83 /* interrupt of Assist debug module, LEVEL*/