Lines Matching +full:0 +full:x3

13 #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
14 #define GD32_DMA_MEMORY_TO_MEMORY      GD32_DMA_CH_CFG_DIRECTION(0)
19 #define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9)
20 #define GD32_DMA_NO_PERIPH_ADDR_INC	     GD32_DMA_CH_CFG_PERIPH_ADDR_INC(0)
24 #define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10)
25 #define GD32_DMA_NO_MEMORY_ADDR_INC	     GD32_DMA_CH_CFG_MEMORY_ADDR_INC(0)
29 #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
30 #define GD32_DMA_PERIPH_WIDTH_8BIT	  GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
35 #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13)
36 #define GD32_DMA_MEMORY_WIDTH_8BIT	  GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
41 #define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15)
43 /* priority defined on bits 16-17 as 0, 1, 2, 3 */
44 #define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16)
45 #define GD32_DMA_PRIORITY_LOW	      GD32_DMA_CH_CFG_PRIORITY(0)