Lines Matching +full:0 +full:x58
12 #define TI_DM_TIMER_TIDR (0x00)
13 #define TI_DM_TIMER_TIOCP_CFG (0x10)
14 #define TI_DM_TIMER_IRQ_EOI (0x20)
15 #define TI_DM_TIMER_IRQSTATUS_RAW (0x24)
16 #define TI_DM_TIMER_IRQSTATUS (0x28) /* Interrupt status register */
17 #define TI_DM_TIMER_IRQENABLE_SET (0x2c) /* Interrupt enable register */
18 #define TI_DM_TIMER_IRQENABLE_CLR (0x30) /* Interrupt disable register */
19 #define TI_DM_TIMER_IRQWAKEEN (0x34)
20 #define TI_DM_TIMER_TCLR (0x38) /* Control register */
21 #define TI_DM_TIMER_TCRR (0x3c) /* Counter register */
22 #define TI_DM_TIMER_TLDR (0x40) /* Load register */
23 #define TI_DM_TIMER_TTGR (0x44)
24 #define TI_DM_TIMER_TWPS (0x48)
25 #define TI_DM_TIMER_TMAR (0x4c) /* Match register */
26 #define TI_DM_TIMER_TCAR1 (0x50)
27 #define TI_DM_TIMER_TSICR (0x54)
28 #define TI_DM_TIMER_TCAR2 (0x58)
29 #define TI_DM_TIMER_TPIR (0x5c)
30 #define TI_DM_TIMER_TNIR (0x60)
31 #define TI_DM_TIMER_TCVR (0x64)
32 #define TI_DM_TIMER_TOCR (0x68)
33 #define TI_DM_TIMER_TOWR (0x6c)
35 #define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT (0)
36 #define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_MASK (0x00000001)
39 #define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_MASK (0x00000002)
42 #define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_MASK (0x00000004)
44 #define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_SHIFT (0)
45 #define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_MASK (0x00000001)
48 #define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_MASK (0x00000002)
51 #define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_MASK (0x00000004)
53 #define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_SHIFT (0)
54 #define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_MASK (0x00000001)
57 #define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_MASK (0x00000002)
60 #define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_MASK (0x00000004)
62 #define TI_DM_TIMER_TCLR_ST_SHIFT (0)
63 #define TI_DM_TIMER_TCLR_ST_MASK (0x00000001)
66 #define TI_DM_TIMER_TCLR_AR_MASK (0x00000002)
69 #define TI_DM_TIMER_TCLR_PTV_MASK (0x0000001c)
72 #define TI_DM_TIMER_TCLR_PRE_MASK (0x00000020)
75 #define TI_DM_TIMER_TCLR_CE_MASK (0x00000040)
78 #define TI_DM_TIMER_TCLR_SCPWM_MASK (0x00000080)
81 #define TI_DM_TIMER_TCLR_TCM_MASK (0x00000300)
84 #define TI_DM_TIMER_TCLR_TRG_MASK (0x00000c00)
87 #define TI_DM_TIMER_TCLR_PT_MASK (0x00001000)
90 #define TI_DM_TIMER_TCLR_CAPT_MODE_MASK (0x00002000)
93 #define TI_DM_TIMER_TCLR_GPO_CFG_MASK (0x00004000)
95 #define TI_DM_TIMER_TCRR_TIMER_COUNTER_SHIFT (0)
96 #define TI_DM_TIMER_TCRR_TIMER_COUNTER_MASK (0xffffffff)
98 #define TI_DM_TIMER_TLDR_LOAD_VALUE_SHIFT (0)
99 #define TI_DM_TIMER_TLDR_LOAD_VALUE_MASK (0xffffffff)
101 #define TI_DM_TIMER_TMAR_COMPARE_VALUE_SHIFT (0)
102 #define TI_DM_TIMER_TMAR_COMPARE_VALUE_MASK (0xffffffff)