Lines Matching +full:1275 +full:- +full:1994

10  * SPDX-License-Identifier: Apache-2.0
34  * @brief Function called to read a 32-bit word from an endpoint's configuration space.
36  * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
48  * @brief Function called to write a 32-bit word to an endpoint's configuration space.
50  * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
75  * @param bar_bus_addr bus-centric address allocated to be written in the BAR register
94  * @param bar_base_addr bus-centric address allocation base
102  * @brief Function called to translate an endpoint Base Address Register bus-centric address
108  * The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
116  * @param bar_bus_addr bus-centric address written in the BAR register
117  * @param bar_addr CPU-centric address translated from the bus-centric address
130  * @brief Read a 32-bit word from a Memory-Mapped endpoint's configuration space.
132  * Read a 32-bit word from an endpoint's configuration space from a Memory-Mapped
136  * @param cfg_addr Logical address of Memory-Mapped configuration space
145  * @brief Write a 32-bit word to a Memory-Mapped endpoint's configuration space.
147  * Write a 32-bit word to an endpoint's configuration space from a Memory-Mapped
151  * @param cfg_addr Logical address of Memory-Mapped configuration space
163  * When on non-x86 architecture or when firmware didn't setup the PCIe Bus hierarchy,
186  * @brief Read a 32-bit word from an endpoint's configuration space.
188  * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
200 		(const struct pcie_ctrl_driver_api *)dev->api;  in pcie_ctrl_conf_read()
202 	return api->conf_read(dev, bdf, reg);  in pcie_ctrl_conf_read()
206  * @brief Write a 32-bit word to an endpoint's configuration space.
208  * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
220 		(const struct pcie_ctrl_driver_api *)dev->api;  in pcie_ctrl_conf_write()
222 	api->conf_write(dev, bdf, reg, data);  in pcie_ctrl_conf_write()
239  * @param bar_bus_addr bus-centric address allocated to be written in the BAR register
247 		(const struct pcie_ctrl_driver_api *)dev->api;  in pcie_ctrl_region_allocate()
249 	return api->region_allocate(dev, bdf, mem, mem64, bar_size, bar_bus_addr);  in pcie_ctrl_region_allocate()
264  * @param bar_base_addr bus-centric address allocation base
272 		(const struct pcie_ctrl_driver_api *)dev->api;  in pcie_ctrl_region_get_allocate_base()
274 	return api->region_get_allocate_base(dev, bdf, mem, mem64, align, bar_base_addr);  in pcie_ctrl_region_get_allocate_base()
278  * @brief Translate an endpoint Base Address Register bus-centric address into Physical address.
283  * The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
291  * @param bar_bus_addr bus-centric address written in the BAR register
292  * @param bar_addr CPU-centric address translated from the bus-centric address
300 		(const struct pcie_ctrl_driver_api *)dev->api;  in pcie_ctrl_region_translate()
302 	if (!api->region_translate) {  in pcie_ctrl_region_translate()
306 		return api->region_translate(dev, bdf, mem, mem64, bar_bus_addr, bar_addr);  in pcie_ctrl_region_translate()
315 		(const struct pcie_ctrl_driver_api *)dev->api;  in pcie_ctrl_msi_device_setup()
317 	return api->msi_device_setup(dev, priority, vectors, n_vector);  in pcie_ctrl_msi_device_setup()
335 		/* Flags as defined in the PCI Bus Binding to IEEE Std 1275-1994 */
337 		/* bus-centric offset from the start of the region */
339 		/* CPU-centric offset from the start of the region */