Lines Matching +full:addr +full:- +full:range
4 * SPDX-License-Identifier: Apache-2.0
31 * @brief Enable the d-cache
38 * @brief Disable the d-cache
45 * @brief Flush the d-cache
50 * @retval -ENOTSUP If not supported.
51 * @retval -errno Negative errno for other failures.
56 * @brief Invalidate the d-cache
61 * @retval -ENOTSUP If not supported.
62 * @retval -errno Negative errno for other failures.
67 * @brief Flush and Invalidate the d-cache
72 * @retval -ENOTSUP If not supported.
73 * @retval -errno Negative errno for other failures.
78 * @brief Flush an address range in the d-cache
80 * Flush the specified address range of the data cache.
85 * not a problem because writing back is a non-destructive process that
87 * @p addr or a padded @p size is not strictly necessary.
89 * @param addr Starting address to flush.
90 * @param size Range size.
93 * @retval -ENOTSUP If not supported.
94 * @retval -errno Negative errno for other failures.
96 int cache_data_flush_range(void *addr, size_t size);
99 * @brief Invalidate an address range in the d-cache
101 * Invalidate the specified address range of the data cache.
105 * non-read-only data structures sharing the same line will be
107 * data loss and/or corruption. When @p addr is not aligned to the cache
111 * @param addr Starting address to invalidate.
112 * @param size Range size.
115 * @retval -ENOTSUP If not supported.
116 * @retval -errno Negative errno for other failures.
118 int cache_data_invd_range(void *addr, size_t size);
121 * @brief Flush and Invalidate an address range in the d-cache
123 * Flush and Invalidate the specified address range of the data cache.
129 * non-destructive process that could be triggered by hardware at any
130 * time, so having an aligned @p addr or a padded @p size is not strictly
133 * @param addr Starting address to flush and invalidate.
134 * @param size Range size.
137 * @retval -ENOTSUP If not supported.
138 * @retval -errno Negative errno for other failures.
140 int cache_data_flush_and_invd_range(void *addr, size_t size);
145 * @brief Get the d-cache line size.
153 * @retval size Size of the d-cache line.
154 * @retval 0 If the d-cache is not enabled.
165 * @brief Enable the i-cache
172 * @brief Disable the i-cache
179 * @brief Flush the i-cache
184 * @retval -ENOTSUP If not supported.
185 * @retval -errno Negative errno for other failures.
190 * @brief Invalidate the i-cache
195 * @retval -ENOTSUP If not supported.
196 * @retval -errno Negative errno for other failures.
201 * @brief Flush and Invalidate the i-cache
206 * @retval -ENOTSUP If not supported.
207 * @retval -errno Negative errno for other failures.
212 * @brief Flush an address range in the i-cache
214 * Flush the specified address range of the instruction cache.
219 * not a problem because writing back is a non-destructive process that
221 * @p addr or a padded @p size is not strictly necessary.
223 * @param addr Starting address to flush.
224 * @param size Range size.
227 * @retval -ENOTSUP If not supported.
228 * @retval -errno Negative errno for other failures.
230 int cache_instr_flush_range(void *addr, size_t size);
233 * @brief Invalidate an address range in the i-cache
235 * Invalidate the specified address range of the instruction cache.
239 * non-read-only data structures sharing the same line will be
241 * data loss and/or corruption. When @p addr is not aligned to the cache
245 * @param addr Starting address to invalidate.
246 * @param size Range size.
249 * @retval -ENOTSUP If not supported.
250 * @retval -errno Negative errno for other failures.
252 int cache_instr_invd_range(void *addr, size_t size);
255 * @brief Flush and Invalidate an address range in the i-cache
257 * Flush and Invalidate the specified address range of the instruction cache.
263 * non-destructive process that could be triggered by hardware at any
264 * time, so having an aligned @p addr or a padded @p size is not strictly
267 * @param addr Starting address to flush and invalidate.
268 * @param size Range size.
271 * @retval -ENOTSUP If not supported.
272 * @retval -errno Negative errno for other failures.
274 int cache_instr_flush_and_invd_range(void *addr, size_t size);
279 * @brief Get the i-cache line size.
287 * @retval size Size of the d-cache line.
288 * @retval 0 If the d-cache is not enabled.