Lines Matching +full:memory +full:- +full:to +full:- +full:memory

4  * SPDX-License-Identifier: Apache-2.0
13  * @defgroup xtensa_mmu_apis Xtensa Memory Management Unit (MMU) APIs
19  * @name Memory region permission and caching mode.
23 /** Memory region is executable. */
26 /** Memory region is writable. */
29 /** Memory region is both executable and writable */
32 /** Memory region has write-back cache. */
35 /** Memory region has write-through cache. */
43  * @name Memory domain and partitions
53 /* Read-Write access permission attributes */
65 /* Execution-allowed attributes */
74  * @brief Software only bit to indicate a memory region can be accessed by user thread(s).
76  * This BIT tells the mapping code which ring PTE entries to use.
81  * @brief Software only bit to indicate a memory region is shared by all threads.
83  * This BIT tells the mapping code whether the memory region should
87  * The PTE mapping this memory will use an ASID that is set in the
93  * Struct used to map a memory region.
96 	/** Name of the memory region. */
99 	/** Start address of the memory region. */
102 	/** End address of the memory region. */
105 	/** Attributes for the memory region. */
110  * @brief Additional memory regions required by SoC.
112  * These memory regions will be setup by MMU initialization code at boot.
116 /** Number of SoC additional memory regions. */
122  * This initializes the MMU hardware and setup the memory regions at boot.
127  * @brief Re-initialize hardware MMU.
130  * re-started.
132  * It assumes that the page table is already created and accessible in memory.
137  * @brief Tell other processors to flush TLBs.
139  * This sends IPI to other processors to telling them to
140  * invalidate cache to page tables and flush TLBs. This is
144  * @note This needs to be implemented in the SoC layer.
149  * @brief Invalidate cache to page tables and flush TLBs.
151  * This invalidates cache to all page tables and flush TLBs