Lines Matching +full:address +full:- +full:length

2  * Copyright (c) 2011-2014, Wind River Systems, Inc.
3  * Copyright (c) 2019-2020 Intel Corp.
5  * SPDX-License-Identifier: Apache-2.0
11  * By default, the kernel is linked at its physical address and all addresses
17  * in RAM and are copied from flash at boot. Text/rodata linked in-place in
21  * LMA for all sections relative to physical address. The virtual address VMAs
22  * for all sections are relative to the base virtual address for the kernel.
23  * Setting LMAs here helps let QEMU or any other ELF-aware loader know where to
38 /* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily
44 #define KERNEL_RAM_SIZE   (CONFIG_KERNEL_VM_SIZE - CONFIG_KERNEL_VM_OFFSET)
45 #define PHYS_RAM_AVAIL    (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
48 #define KERNEL_RAM_SIZE   (PHYS_RAM_SIZE - CONFIG_SRAM_OFFSET)
61    * Board-level DTS must specify a flash region that doesn't overlap with
64   #define FLASH_ROM_SIZE      (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - ROM_END_OFFSET)
76 #define LOCORE_SIZE         (0x10000 - LOCORE_BASE)
79 #error Virtual kernel linking is not yet implemented for 64-bit
86     /* Address range where the kernel will be installed on a flash part (XIP),
89     ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = FLASH_ROM_SIZE
91     ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_AVAIL
93     /* Linear address range to link the kernel. If non-XIP, everything is
97     RAM (wx)        : ORIGIN = KERNEL_BASE_ADDR, LENGTH = KERNEL_RAM_SIZE
101     /* Special low-memory area for bootstrapping other CPUs from real mode */
102     LOCORE (wx)     : ORIGIN = LOCORE_BASE, LENGTH = LOCORE_SIZE
105      * On 32-bit x86, fake memory area for build-time IDT generation data.
106      * 64-bit doesn't use this, interrupts are all managed at runtime.
109      * final ELF image. The address doesn't even have to be valid on the
113     IDT_LIST        : ORIGIN = 0xFFFF1000, LENGTH = 2K