Lines Matching +full:enable +full:- +full:fault +full:- +full:queue
3 * SPDX-License-Identifier: Apache-2.0
22 #define VTD_FSTS_REG 0x034 /* Fault Status */
23 #define VTD_FECTL_REG 0x038 /* Fault Event Control */
24 #define VTD_FEDATA_REG 0x03C /* Fault Event Data */
25 #define VTD_FEADDR_REG 0x040 /* Fault Event Address */
26 #define VTD_FEUADDR_REG 0x044 /* Fault Event Upper Address */
27 #define VTD_AFLOG_REG 0x058 /* Advanced Fault Log */
28 #define VTD_PMEN_REG 0x064 /* Protected Memory Enable */
33 #define VTD_IQH_REG 0x080 /* Invalidation Queue Head */
34 #define VTD_IQT_REG 0x088 /* Invalidation Queue Tail */
35 #define VTD_IQA_REG 0x090 /* Invalidation Queue Address */
41 #define VTD_IQERCD_REG 0x0B0 /* Invalidation Queue Error Record */
43 #define VTD_PQH_REG 0x0C0 /* Page Request Queue Head */
44 #define VTD_PQT_REG 0x0C8 /* Page Request Queue Tail */
45 #define VTD_PQA_REG 0x0D0 /* Page Request Queue Address */
53 #define VTD_MTRR_FIX64K_00000_REG 0x120 /* Fixed-range MTRR for 64K_00000 */
54 #define VTD_MTRR_FIX16K_80000_REG 0x128 /* Fixed-range MTRR for 16K_80000 */
55 #define VTD_MTRR_FIX16K_A0000_REG 0x130 /* Fixed-range MTRR for 16K_A0000 */
56 #define VTD_MTRR_FIX4K_C0000_REG 0x138 /* Fixed-range MTRR for 4K_C0000 */
57 #define VTD_MTRR_FIX4K_C8000_REG 0x140 /* Fixed-range MTRR for 4K_C8000 */
58 #define VTD_MTRR_FIX4K_D0000_REG 0x148 /* Fixed-range MTRR for 4K_D0000 */
59 #define VTD_MTRR_FIX4K_D8000_REG 0x150 /* Fixed-range MTRR for 4K_D8000 */
60 #define VTD_MTRR_FIX4K_E0000_REG 0x158 /* Fixed-range MTRR for 4K_E0000 */
61 #define VTD_MTRR_FIX4K_E8000_REG 0x160 /* Fixed-range MTRR for 4K_E8000 */
62 #define VTD_MTRR_FIX4K_F0000_REG 0x168 /* Fixed-range MTRR for 4K_F0000 */
63 #define VTD_MTRR_FIX4K_F8000_REG 0x170 /* Fixed-range MTRR for 4K_F8000 */
64 #define VTD_MTRR_PHYSBASE0_REG 0x180 /* Variable-range MTRR Base0 */
65 #define VTD_MTRR_PHYSMASK0_REG 0x188 /* Variable-range MTRR Mask0 */
66 #define VTD_MTRR_PHYSBASE1_REG 0x190 /* Variable-range MTRR Base1 */
67 #define VTD_MTRR_PHYSMASK1_REG 0x198 /* Variable-range MTRR Mask1 */
68 #define VTD_MTRR_PHYSBASE2_REG 0x1A0 /* Variable-range MTRR Base2 */
69 #define VTD_MTRR_PHYSMASK2_REG 0x1A8 /* Variable-range MTRR Mask2 */
70 #define VTD_MTRR_PHYSBASE3_REG 0x1B0 /* Variable-range MTRR Base3 */
71 #define VTD_MTRR_PHYSMASK3_REG 0x1B8 /* Variable-range MTRR Mask3 */
72 #define VTD_MTRR_PHYSBASE4_REG 0x1C0 /* Variable-range MTRR Base4 */
73 #define VTD_MTRR_PHYSMASK4_REG 0x1C8 /* Variable-range MTRR Mask4 */
74 #define VTD_MTRR_PHYSBASE5_REG 0x1D0 /* Variable-range MTRR Base5 */
75 #define VTD_MTRR_PHYSMASK5_REG 0x1D8 /* Variable-range MTRR Mask5 */
76 #define VTD_MTRR_PHYSBASE6_REG 0x1E0 /* Variable-range MTRR Base6 */
77 #define VTD_MTRR_PHYSMASK6_REG 0x1E8 /* Variable-range MTRR Mask6 */
78 #define VTD_MTRR_PHYSBASE7_REG 0x1F0 /* Variable-range MTRR Base7 */
79 #define VTD_MTRR_PHYSMASK7_REG 0x1F8 /* Variable-range MTRR Mask7 */
80 #define VTD_MTRR_PHYSBASE8_REG 0x200 /* Variable-range MTRR Base8 */
81 #define VTD_MTRR_PHYSMASK8_REG 0x208 /* Variable-range MTRR Mask8 */
82 #define VTD_MTRR_PHYSBASE9_REG 0x210 /* Variable-range MTRR Base9 */
83 #define VTD_MTRR_PHYSMASK9_REG 0x218 /* Variable-range MTRR Mask9 */
131 /* Fault event control register details */
135 /* Fault event status register details */
156 /* Fault recording register(s) details
168 #define VTD_FRCD_FR(fault) \ argument
169 ((uint8_t)((fault & VTD_FRCD_FR_MASK) >> VTD_FRCD_FR_POS))
172 #define VTD_FRCD_SID(fault) \ argument
173 ((uint16_t)(fault & VTD_FRCD_SID_MASK))
178 #define VTD_FRCD_FI(fault) \ argument
179 ((fault & VTD_FRCD_FI_MASK) >> VTD_FRCD_FI_POS)
183 #define VTD_FRCD_FI_IR(fault) \ argument
184 ((fault & VTD_FRCD_FI_IR_MASK) >> VTD_FRCD_FI_IR_POS)
186 /* Invalidation Queue Address register details */
193 /* Invalidation Queue Head register details */
197 /* Invalidation Queue Tail register details */