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2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief IA-32 specific kernel interface header
10 * This header contains the IA-32 specific kernel interface. It is included
78 /** IRQ associated with the ISR/stub, or -1 if this is not
80 * not be -1
83 /** Priority associated with the IRQ. Ignored if vec is not -1 */
85 /** Vector number associated with ISR/stub, or -1 to assign based
104 * vector, @a v using the descriptor privilege level @a d. On the IA-32
111 * The @a d argument specifies the privilege level for the interrupt-gate
113 * whereas handlers for user-mode software generated interrupts should specify 3.
166 * at build time; instead the sentinel value -1 is saved, and gen_idt figures
172 #define _VECTOR_ARG(irq_p) (-1)
196 * between the vector and the IRQ line as well as triggering flags
202 ".long %c[isr]_irq%c[irq]_stub\n\t" /* ISR_LIST.fnc */ \
203 ".long %c[irq]\n\t" /* ISR_LIST.irq */ \
204 ".long %c[priority]\n\t" /* ISR_LIST.priority */ \
205 ".long %c[vector]\n\t" /* ISR_LIST.vec */ \
206 ".long 0\n\t" /* ISR_LIST.dpl */ \
207 ".long 0\n\t" /* ISR_LIST.tss */ \
235 * all non-user accessible pages in the page table are marked non-present.
244 NANO_CPU_INT_REGISTER(isr_p, irq_p, priority_p, -1, 0); \
299 --_kernel.cpus[0].nested; in arch_isr_direct_footer()
350 * correspond to any IRQ line (such as spurious vector or SW IRQ)
352 #define NANO_SOFT_IRQ ((unsigned int) (-1))