Lines Matching +full:1 +full:- +full:a
3 * SPDX-License-Identifier: Apache-2.0
13 /* The standard RISC-V atomic-instruction extension, "A", specifies
14 * the number of instructions that atomically read-modify-write memory,
15 * which RISC-V harts should support in order to synchronise harts
16 * running in the same memory space. This is the subset of RISC-V
17 * atomic-instructions not present in atomic_builtin.h file.
25 __asm__ volatile("amoswap.d.aq %0, %1, %2" in atomic_swap()
27 : "r"(newval), "A"(*target) in atomic_swap()
37 __asm__ volatile("amomax.d.aq %0, %1, %2" in atomic_max()
39 : "r"(value), "A"(*target) in atomic_max()
49 __asm__ volatile("amomin.d.aq %0, %1, %2" in atomic_min()
51 : "r"(value), "A"(*target) in atomic_min()
61 __asm__ volatile("amomaxu.d.aq %0, %1, %2" in atomic_maxu()
63 : "r"(value), "A"(*target) in atomic_maxu()
73 __asm__ volatile("amominu.d.aq %0, %1, %2" in atomic_minu()
75 : "r"(value), "A"(*target) in atomic_minu()
87 __asm__ volatile("amoswap.w.aq %0, %1, %2"
89 : "r"(newval), "A"(*target)
99 __asm__ volatile("amomax.w.aq %0, %1, %2"
101 : "r"(value), "A"(*target)
111 __asm__ volatile("amomin.w.aq %0, %1, %2"
113 : "r"(value), "A"(*target)
123 __asm__ volatile("amomaxu.w.aq %0, %1, %2"
125 : "r"(value), "A"(*target)
135 __asm__ volatile("amominu.w.aq %0, %1, %2"
137 : "r"(value), "A"(*target)