4  * SPDX-License-Identifier: Apache-2.0
31  * @brief Enable the d-cache
40  * @brief Disable the d-cache
49  * @brief Flush the d-cache
54  * @retval -ENOTSUP If not supported.
55  * @retval -errno Negative errno for other failures.
62  * @brief Invalidate the d-cache
67  * @retval -ENOTSUP If not supported.
68  * @retval -errno Negative errno for other failures.
75  * @brief Flush and Invalidate the d-cache
80  * @retval -ENOTSUP If not supported.
81  * @retval -errno Negative errno for other failures.
88  * @brief Flush an address range in the d-cache
90  * Flush the specified address range of the data cache.
95  *       not a problem because writing back is a non-destructive process that
97  *       @p addr or a padded @p size is not strictly necessary.
99  * @param addr Starting address to flush.
100  * @param size Range size.
103  * @retval -ENOTSUP If not supported.
104  * @retval -errno Negative errno for other failures.
106 int arch_dcache_flush_range(void *addr, size_t size);
108 #define cache_data_flush_range(addr, size) arch_dcache_flush_range(addr, size)  argument
111  * @brief Invalidate an address range in the d-cache
113  * Invalidate the specified address range of the data cache.
117  *       non-read-only data structures sharing the same line will be
119  *       data loss and/or corruption. When @p addr is not aligned to the cache
123  * @param addr Starting address to invalidate.
124  * @param size Range size.
127  * @retval -ENOTSUP If not supported.
128  * @retval -errno Negative errno for other failures.
130 int arch_dcache_invd_range(void *addr, size_t size);
132 #define cache_data_invd_range(addr, size) arch_dcache_invd_range(addr, size)  argument
135  * @brief Flush and Invalidate an address range in the d-cache
137  * Flush and Invalidate the specified address range of the data cache.
143  *       non-destructive process that could be triggered by hardware at any
144  *       time, so having an aligned @p addr or a padded @p size is not strictly
147  * @param addr Starting address to flush and invalidate.
148  * @param size Range size.
151  * @retval -ENOTSUP If not supported.
152  * @retval -errno Negative errno for other failures.
155 int arch_dcache_flush_and_invd_range(void *addr, size_t size);
157 #define cache_data_flush_and_invd_range(addr, size) \  argument
158 	arch_dcache_flush_and_invd_range(addr, size)
164  * @brief Get the d-cache line size.
172  * @retval size Size of the d-cache line.
173  * @retval 0 If the d-cache is not enabled.
186  * @brief Enable the i-cache
195  * @brief Disable the i-cache
204  * @brief Flush the i-cache
209  * @retval -ENOTSUP If not supported.
210  * @retval -errno Negative errno for other failures.
217  * @brief Invalidate the i-cache
222  * @retval -ENOTSUP If not supported.
223  * @retval -errno Negative errno for other failures.
230  * @brief Flush and Invalidate the i-cache
235  * @retval -ENOTSUP If not supported.
236  * @retval -errno Negative errno for other failures.
243  * @brief Flush an address range in the i-cache
245  * Flush the specified address range of the instruction cache.
250  *       not a problem because writing back is a non-destructive process that
252  *       @p addr or a padded @p size is not strictly necessary.
254  * @param addr Starting address to flush.
255  * @param size Range size.
258  * @retval -ENOTSUP If not supported.
259  * @retval -errno Negative errno for other failures.
261 int arch_icache_flush_range(void *addr, size_t size);
263 #define cache_instr_flush_range(addr, size) arch_icache_flush_range(addr, size)  argument
266  * @brief Invalidate an address range in the i-cache
268  * Invalidate the specified address range of the instruction cache.
272  *       non-read-only data structures sharing the same line will be
274  *       data loss and/or corruption. When @p addr is not aligned to the cache
278  * @param addr Starting address to invalidate.
279  * @param size Range size.
282  * @retval -ENOTSUP If not supported.
283  * @retval -errno Negative errno for other failures.
285 int arch_icache_invd_range(void *addr, size_t size);
287 #define cache_instr_invd_range(addr, size) arch_icache_invd_range(addr, size)  argument
290  * @brief Flush and Invalidate an address range in the i-cache
292  * Flush and Invalidate the specified address range of the instruction cache.
298  *       non-destructive process that could be triggered by hardware at any
299  *       time, so having an aligned @p addr or a padded @p size is not strictly
302  * @param addr Starting address to flush and invalidate.
303  * @param size Range size.
306  * @retval -ENOTSUP If not supported.
307  * @retval -errno Negative errno for other failures.
309 int arch_icache_flush_and_invd_range(void *addr, size_t size);
311 #define cache_instr_flush_and_invd_range(addr, size) \  argument
312 	arch_icache_flush_and_invd_range(addr, size)
318  * @brief Get the i-cache line size.
326  * @retval size Size of the d-cache line.
327  * @retval 0 If the d-cache is not enabled.