97  *       @p addr or a padded @p size is not strictly necessary.
100  * @param size Range size.
106 int arch_dcache_flush_range(void *addr, size_t size);
108 #define cache_data_flush_range(addr, size) arch_dcache_flush_range(addr, size)  argument
120  *       line and/or @p size is not a multiple of the cache line size the
124  * @param size Range size.
130 int arch_dcache_invd_range(void *addr, size_t size);
132 #define cache_data_invd_range(addr, size) arch_dcache_invd_range(addr, size)  argument
144  *       time, so having an aligned @p addr or a padded @p size is not strictly
148  * @param size Range size.
155 int arch_dcache_flush_and_invd_range(void *addr, size_t size);
157 #define cache_data_flush_and_invd_range(addr, size) \  argument
158 	arch_dcache_flush_and_invd_range(addr, size)
164  * @brief Get the d-cache line size.
166  * The API is provided to dynamically detect the data cache line size at run
172  * @retval size Size of the d-cache line.
252  *       @p addr or a padded @p size is not strictly necessary.
255  * @param size Range size.
261 int arch_icache_flush_range(void *addr, size_t size);
263 #define cache_instr_flush_range(addr, size) arch_icache_flush_range(addr, size)  argument
275  *       line and/or @p size is not a multiple of the cache line size the
279  * @param size Range size.
285 int arch_icache_invd_range(void *addr, size_t size);
287 #define cache_instr_invd_range(addr, size) arch_icache_invd_range(addr, size)  argument
299  *       time, so having an aligned @p addr or a padded @p size is not strictly
303  * @param size Range size.
309 int arch_icache_flush_and_invd_range(void *addr, size_t size);
311 #define cache_instr_flush_and_invd_range(addr, size) \  argument
312 	arch_icache_flush_and_invd_range(addr, size)
318  * @brief Get the i-cache line size.
320  * The API is provided to dynamically detect the instruction cache line size at
326  * @retval size Size of the d-cache line.