Lines Matching refs:BIT
13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
24 #define DAIF_IRQ_BIT BIT(7)
25 #define DAIF_ABT_BIT BIT(8)
26 #define DAIF_DBG_BIT BIT(9)
39 #define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
40 BIT(22) | BIT(18) | BIT(16) | \
41 BIT(11) | BIT(5) | BIT(4))
43 #define SCTLR_EL2_RES1 (BIT(29) | BIT(28) | BIT(23) | \
44 BIT(22) | BIT(18) | BIT(16) | \
45 BIT(11) | BIT(5) | BIT(4))
47 #define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
48 BIT(22) | BIT(20) | BIT(11))
50 #define SCTLR_M_BIT BIT(0)
51 #define SCTLR_A_BIT BIT(1)
52 #define SCTLR_C_BIT BIT(2)
53 #define SCTLR_SA_BIT BIT(3)
54 #define SCTLR_I_BIT BIT(12)
55 #define SCTLR_BR_BIT BIT(17)
59 #define SCR_NS_BIT BIT(0)
60 #define SCR_IRQ_BIT BIT(1)
61 #define SCR_FIQ_BIT BIT(2)
62 #define SCR_EA_BIT BIT(3)
63 #define SCR_SMD_BIT BIT(7)
64 #define SCR_HCE_BIT BIT(8)
65 #define SCR_RW_BIT BIT(10)
66 #define SCR_ST_BIT BIT(11)
67 #define SCR_EEL2_BIT BIT(18)
69 #define SCR_RES1 (BIT(4) | BIT(5))
108 #define CNTV_CTL_ENABLE_BIT BIT(0)
109 #define CNTV_CTL_IMASK_BIT BIT(1)
124 #define ACTLR_EL3_CPUACTLR_BIT BIT(0)
125 #define ACTLR_EL3_CPUECTLR_BIT BIT(1)
126 #define ACTLR_EL3_L2CTLR_BIT BIT(4)
127 #define ACTLR_EL3_L2ECTLR_BIT BIT(5)
128 #define ACTLR_EL3_L2ACTLR_BIT BIT(6)
130 #define CPTR_EZ_BIT BIT(8)
131 #define CPTR_TFP_BIT BIT(10)
132 #define CPTR_TTA_BIT BIT(20)
133 #define CPTR_TCPAC_BIT BIT(31)
135 #define CPTR_EL2_RES1 BIT(13) | BIT(12) | BIT(9) | (0xff)
137 #define HCR_FMO_BIT BIT(3)
138 #define HCR_IMO_BIT BIT(4)
139 #define HCR_AMO_BIT BIT(5)
140 #define HCR_TGE_BIT BIT(27)
141 #define HCR_RW_BIT BIT(31)
164 #define ICC_SRE_ELx_SRE_BIT BIT(0)
165 #define ICC_SRE_ELx_DFB_BIT BIT(1)
166 #define ICC_SRE_ELx_DIB_BIT BIT(2)
167 #define ICC_SRE_EL3_EN_BIT BIT(3)
207 #define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI_BIT BIT(6)
212 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)