Lines Matching +full:gpio +full:- +full:cells
3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
34 #interrupt-cells = <3>;
36 interrupt-controller;
42 interrupt-controller;
43 #interrupt-cells = <3>;
44 #address-cells = <1>;
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "pcie-controller";
51 acpi-hid = "PNP0A08";
55 compatible = "intel,pch-smbus";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 vendor-id = <0x8086>;
59 device-id = <0x7a23>;
61 interrupt-parent = <&intc>;
68 #dma-cells = <1>;
73 compatible = "snps,designware-i2c";
74 clock-frequency = <I2C_BITRATE_STANDARD>;
75 #address-cells = <1>;
76 #size-cells = <0>;
77 vendor-id = <0x8086>;
78 device-id = <0x7acc>;
80 interrupt-parent = <&intc>;
88 #dma-cells = <1>;
93 compatible = "snps,designware-i2c";
94 clock-frequency = <I2C_BITRATE_STANDARD>;
95 #address-cells = <1>;
96 #size-cells = <0>;
97 vendor-id = <0x8086>;
98 device-id = <0x7acd>;
100 interrupt-parent = <&intc>;
108 #dma-cells = <1>;
113 compatible = "snps,designware-i2c";
114 clock-frequency = <I2C_BITRATE_STANDARD>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 #address-cells = <1>;
118 #size-cells = <0>;
119 vendor-id = <0x8086>;
120 device-id = <0x7ace>;
122 interrupt-parent = <&intc>;
130 #dma-cells = <1>;
135 compatible = "snps,designware-i2c";
136 clock-frequency = <I2C_BITRATE_STANDARD>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 vendor-id = <0x8086>;
140 device-id = <0x7acf>;
142 interrupt-parent = <&intc>;
150 #dma-cells = <1>;
155 compatible = "snps,designware-i2c";
156 clock-frequency = <I2C_BITRATE_STANDARD>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 vendor-id = <0x8086>;
160 device-id = <0x7afc>;
162 interrupt-parent = <&intc>;
170 #dma-cells = <1>;
175 compatible = "snps,designware-i2c";
176 clock-frequency = <I2C_BITRATE_STANDARD>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 vendor-id = <0x8086>;
180 device-id = <0x7afd>;
182 interrupt-parent = <&intc>;
190 #dma-cells = <1>;
195 compatible = "snps,designware-i2c";
196 clock-frequency = <I2C_BITRATE_STANDARD>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 vendor-id = <0x8086>;
200 device-id = <0x7ada>;
202 interrupt-parent = <&intc>;
210 #dma-cells = <1>;
215 compatible = "snps,designware-i2c";
216 clock-frequency = <I2C_BITRATE_STANDARD>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 vendor-id = <0x8086>;
220 device-id = <0x7adb>;
222 interrupt-parent = <&intc>;
229 compatible = "intel,penwell-spi";
230 vendor-id = <0x8086>;
231 device-id = <0x7aaa>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 pw,cs-mode = <0>;
235 pw,cs-output = <0>;
236 pw,fifo-depth = <64>;
237 cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>;
238 clock-frequency = <100000000>;
240 interrupt-parent = <&intc>;
245 compatible = "intel,penwell-spi";
246 vendor-id = <0x8086>;
247 device-id = <0x7aab>;
248 #address-cells = <1>;
249 #size-cells = <0>;
250 pw,cs-mode = <0>;
251 pw,cs-output = <0>;
252 pw,fifo-depth = <64>;
253 cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>;
254 clock-frequency = <100000000>;
256 interrupt-parent = <&intc>;
261 compatible = "intel,penwell-spi";
262 vendor-id = <0x8086>;
263 device-id = <0x7afb>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 pw,cs-mode = <0>;
267 pw,cs-output = <0>;
268 pw,fifo-depth = <64>;
269 cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>;
270 clock-frequency = <100000000>;
272 interrupt-parent = <&intc>;
278 #dma-cells = <1>;
284 vendor-id = <0x8086>;
285 device-id = <0x7aa8>;
286 reg-shift = <2>;
287 clock-frequency = <1843200>;
289 interrupt-parent = <&intc>;
290 current-speed = <115200>;
292 dma-names = "tx", "rx";
298 #dma-cells = <1>;
304 vendor-id = <0x8086>;
305 device-id = <0x7aa9>;
306 reg-shift = <2>;
307 clock-frequency = <1843200>;
309 interrupt-parent = <&intc>;
310 current-speed = <115200>;
312 dma-names = "tx", "rx";
318 vendor-id = <0x8086>;
319 device-id = <0x7afe>;
320 reg-shift = <2>;
321 clock-frequency = <1843200>;
323 interrupt-parent = <&intc>;
324 current-speed = <115200>;
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "simple-bus";
336 compatible = "intel,vt-d";
345 io-mapped;
346 clock-frequency = <1843200>;
348 interrupt-parent = <&intc>;
349 reg-shift = <0>;
350 io-mapped;
354 gpio_0_i: gpio@e06e0700 {
355 compatible = "intel,gpio";
358 interrupt-parent = <&intc>;
359 group-index = <0x0>;
360 gpio-controller;
361 #gpio-cells = <2>;
363 pin-offset = <0>;
368 gpio_0_r: gpio@e06e0890 {
369 compatible = "intel,gpio";
372 interrupt-parent = <&intc>;
373 group-index = <0x1>;
374 gpio-controller;
375 #gpio-cells = <2>;
377 pin-offset = <26>;
382 gpio_0_j: gpio@e06e0a00 {
383 compatible = "intel,gpio";
386 interrupt-parent = <&intc>;
387 group-index = <0x2>;
388 gpio-controller;
389 #gpio-cells = <2>;
391 pin-offset = <49>;
396 gpio_1_b: gpio@e06d0700 {
397 compatible = "intel,gpio";
400 interrupt-parent = <&intc>;
401 group-index = <0x0>;
402 gpio-controller;
403 #gpio-cells = <2>;
405 pin-offset = <0>;
410 gpio_1_g: gpio@e06d0880 {
411 compatible = "intel,gpio";
414 interrupt-parent = <&intc>;
415 group-index = <0x1>;
416 gpio-controller;
417 #gpio-cells = <2>;
419 pin-offset = <24>;
424 gpio_1_h: gpio@e06d0900 {
425 compatible = "intel,gpio";
428 interrupt-parent = <&intc>;
429 group-index = <0x2>;
430 gpio-controller;
431 #gpio-cells = <2>;
433 pin-offset = <32>;
438 gpio_3_a: gpio@e06b0790 {
439 compatible = "intel,gpio";
442 interrupt-parent = <&intc>;
443 group-index = <0x1>;
444 gpio-controller;
445 #gpio-cells = <2>;
447 pin-offset = <9>;
452 gpio_3_c: gpio@e06b0890 {
453 compatible = "intel,gpio";
456 interrupt-parent = <&intc>;
457 group-index = <0x2>;
458 gpio-controller;
459 #gpio-cells = <2>;
461 pin-offset = <25>;
466 gpio_4_s: gpio@e06a0700 {
467 compatible = "intel,gpio";
470 interrupt-parent = <&intc>;
471 group-index = <0x0>;
472 gpio-controller;
473 #gpio-cells = <2>;
475 pin-offset = <0>;
480 gpio_4_e: gpio@e06a0780 {
481 compatible = "intel,gpio";
484 interrupt-parent = <&intc>;
485 group-index = <0x1>;
486 gpio-controller;
487 #gpio-cells = <2>;
489 pin-offset = <8>;
494 gpio_4_k: gpio@e06a08f0 {
495 compatible = "intel,gpio";
498 interrupt-parent = <&intc>;
499 group-index = <0x2>;
500 gpio-controller;
501 #gpio-cells = <2>;
503 pin-offset = <25>;
508 gpio_4_f: gpio@e06a09e0 {
509 compatible = "intel,gpio";
512 interrupt-parent = <&intc>;
513 group-index = <0x3>;
514 gpio-controller;
515 #gpio-cells = <2>;
517 pin-offset = <41>;
522 gpio_5_d: gpio@e0690700 {
523 compatible = "intel,gpio";
526 interrupt-parent = <&intc>;
527 group-index = <0x0>;
528 gpio-controller;
529 #gpio-cells = <2>;
531 pin-offset = <0>;
537 compatible = "intel,blinky-pwm";
539 reg-offset = <0x304>;
540 clock-frequency = <32768>;
541 max-pins = <1>;
542 #pwm-cells = <2>;
550 interrupt-parent = <&intc>;
551 alarms-count = <1>;
557 compatible = "intel,timeaware-gpio";
559 timer-clock = <19200000>;
560 max-pins = <2>;
568 interrupt-parent = <&intc>;
574 compatible = "intel,tco-wdt";