Lines Matching +full:vendor +full:- +full:id
3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
34 #interrupt-cells = <3>;
40 interrupt-controller;
41 #interrupt-cells = <3>;
42 #address-cells = <1>;
46 compatible = "pcie-controller";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 acpi-hid = "PNP0A08";
53 compatible = "intel,pch-smbus";
54 #address-cells = <1>;
55 #size-cells = <0>;
56 vendor-id = <0x8086>;
57 device-id = <0x51a3>;
59 interrupt-parent = <&intc>;
66 vendor-id = <0x8086>;
67 device-id = <0x51a8>;
68 reg-shift = <2>;
69 clock-frequency = <1843200>;
71 interrupt-parent = <&intc>;
72 current-speed = <115200>;
79 vendor-id = <0x8086>;
80 device-id = <0x51A9>;
81 reg-shift = <2>;
82 clock-frequency = <1843200>;
84 interrupt-parent = <&intc>;
85 current-speed = <115200>;
91 compatible = "intel,penwell-spi";
92 #address-cells = <1>;
93 #size-cells = <0>;
94 vendor-id = <0x8086>;
95 device-id = <0x51aa>;
96 pw,cs-mode = <0>;
97 pw,cs-output = <0>;
98 pw,fifo-depth = <64>;
99 cs-gpios = <&gpio_4_e 10 GPIO_ACTIVE_LOW>;
100 clock-frequency = <100000000>;
102 interrupt-parent = <&intc>;
108 compatible = "intel,penwell-spi";
109 #address-cells = <1>;
110 #size-cells = <0>;
111 vendor-id = <0x8086>;
112 device-id = <0x51ab>;
113 pw,cs-mode = <0>;
114 pw,cs-output = <0>;
115 pw,fifo-depth = <64>;
116 cs-gpios = <&gpio_4_f 16 GPIO_ACTIVE_LOW>;
117 clock-frequency = <100000000>;
119 interrupt-parent = <&intc>;
125 compatible = "intel,penwell-spi";
126 #address-cells = <1>;
127 #size-cells = <0>;
128 vendor-id = <0x8086>;
129 device-id = <0x51fb>;
130 pw,cs-mode = <0>;
131 pw,cs-output = <0>;
132 pw,fifo-depth = <64>;
133 cs-gpios = <&gpio_1_d 9 GPIO_ACTIVE_LOW>;
134 clock-frequency = <100000000>;
136 interrupt-parent = <&intc>;
142 compatible = "snps,designware-i2c";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 clock-frequency = <I2C_BITRATE_STANDARD>;
146 vendor-id = <0x8086>;
147 device-id = <0x51e8>;
149 interrupt-parent = <&intc>;
155 compatible = "snps,designware-i2c";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 clock-frequency = <I2C_BITRATE_STANDARD>;
159 vendor-id = <0x8086>;
160 device-id = <0x51e9>;
162 interrupt-parent = <&intc>;
168 compatible = "snps,designware-i2c";
169 #address-cells = <1>;
170 #size-cells = <0>;
171 clock-frequency = <I2C_BITRATE_STANDARD>;
172 vendor-id = <0x8086>;
173 device-id = <0x51ea>;
175 interrupt-parent = <&intc>;
181 compatible = "snps,designware-i2c";
182 #address-cells = <1>;
183 #size-cells = <0>;
184 clock-frequency = <I2C_BITRATE_STANDARD>;
185 vendor-id = <0x8086>;
186 device-id = <0x51eb>;
188 interrupt-parent = <&intc>;
194 compatible = "snps,designware-i2c";
195 #address-cells = <1>;
196 #size-cells = <0>;
197 clock-frequency = <I2C_BITRATE_STANDARD>;
198 vendor-id = <0x8086>;
199 device-id = <0x51c5>;
201 interrupt-parent = <&intc>;
207 compatible = "snps,designware-i2c";
208 #address-cells = <1>;
209 #size-cells = <0>;
210 clock-frequency = <I2C_BITRATE_STANDARD>;
211 vendor-id = <0x8086>;
212 device-id = <0x51c6>;
214 interrupt-parent = <&intc>;
220 compatible = "snps,designware-i2c";
221 #address-cells = <1>;
222 #size-cells = <0>;
223 clock-frequency = <I2C_BITRATE_STANDARD>;
224 vendor-id = <0x8086>;
225 device-id = <0x51d8>;
227 interrupt-parent = <&intc>;
233 compatible = "snps,designware-i2c";
234 #address-cells = <1>;
235 #size-cells = <0>;
236 clock-frequency = <I2C_BITRATE_STANDARD>;
237 vendor-id = <0x8086>;
238 device-id = <0x51d9>;
240 interrupt-parent = <&intc>;
247 compatible = "simple-bus";
248 #address-cells = <1>;
249 #size-cells = <1>;
256 interrupt-parent = <&intc>;
258 group-index = <0x0>;
259 gpio-controller;
260 #gpio-cells = <2>;
263 pin-offset = <0>;
272 interrupt-parent = <&intc>;
274 group-index = <0x1>;
275 gpio-controller;
276 #gpio-cells = <2>;
279 pin-offset = <25>;
288 interrupt-parent = <&intc>;
290 group-index = <0x2>;
291 gpio-controller;
292 #gpio-cells = <2>;
295 pin-offset = <41>;
304 interrupt-parent = <&intc>;
306 group-index = <0x0>;
307 gpio-controller;
308 #gpio-cells = <2>;
311 pin-offset = <0>;
320 interrupt-parent = <&intc>;
322 group-index = <0x1>;
323 gpio-controller;
324 #gpio-cells = <2>;
327 pin-offset = <8>;
337 interrupt-parent = <&intc>;
339 group-index = <0x2>;
340 gpio-controller;
341 #gpio-cells = <2>;
344 pin-offset = <25>;
353 interrupt-parent = <&intc>;
355 group-index = <0x0>;
356 gpio-controller;
357 #gpio-cells = <2>;
360 pin-offset = <0>;
369 interrupt-parent = <&intc>;
371 group-index = <0x0>;
372 gpio-controller;
373 #gpio-cells = <2>;
376 pin-offset = <0>;
385 interrupt-parent = <&intc>;
387 group-index = <0x1>;
388 gpio-controller;
389 #gpio-cells = <2>;
392 pin-offset = <24>;
401 interrupt-parent = <&intc>;
403 group-index = <0x3>;
404 gpio-controller;
405 #gpio-cells = <2>;
408 pin-offset = <57>;
417 interrupt-parent = <&intc>;
419 group-index = <0x0>;
420 gpio-controller;
421 #gpio-cells = <2>;
424 pin-offset = <0>;
430 compatible = "intel,timeaware-gpio";
432 timer-clock = <19200000>;
433 max-pins = <2>;
442 interrupt-parent = <&intc>;
443 alarms-count = <1>;
452 interrupt-parent = <&intc>;
458 compatible = "intel,tco-wdt";
465 compatible = "intel,blinky-pwm";
467 reg-offset = <0x204>;
468 clock-frequency = <32768>;
469 max-pins = <1>;
470 #pwm-cells = <2>;