Lines Matching +full:vendor +full:- +full:id
2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
34 #interrupt-cells = <3>;
36 interrupt-controller;
42 interrupt-controller;
43 #interrupt-cells = <3>;
44 #address-cells = <1>;
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "pcie-controller";
51 acpi-hid = "PNP0A08";
57 vendor-id = <0x8086>;
58 device-id = <0x5abc>;
60 reg-shift = <2>;
61 clock-frequency = <1843200>;
63 interrupt-parent = <&intc>;
65 current-speed = <115200>;
71 vendor-id = <0x8086>;
72 device-id = <0x5abe>;
74 reg-shift = <2>;
75 clock-frequency = <1843200>;
77 interrupt-parent = <&intc>;
80 current-speed = <115200>;
86 vendor-id = <0x8086>;
87 device-id = <0x5ac0>;
89 reg-shift = <2>;
90 clock-frequency = <1843200>;
92 interrupt-parent = <&intc>;
95 current-speed = <115200>;
101 vendor-id = <0x8086>;
102 device-id = <0x5aee>;
104 reg-shift = <2>;
105 clock-frequency = <1843200>;
107 interrupt-parent = <&intc>;
110 current-speed = <115200>;
114 compatible = "snps,designware-i2c";
115 clock-frequency = <I2C_BITRATE_STANDARD>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 vendor-id = <0x8086>;
119 device-id = <0x5aac>;
121 interrupt-parent = <&intc>;
127 compatible = "snps,designware-i2c";
128 clock-frequency = <I2C_BITRATE_STANDARD>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 vendor-id = <0x8086>;
132 device-id = <0x5aae>;
134 interrupt-parent = <&intc>;
140 compatible = "snps,designware-i2c";
141 clock-frequency = <I2C_BITRATE_STANDARD>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 vendor-id = <0x8086>;
145 device-id = <0x5ab0>;
147 interrupt-parent = <&intc>;
153 compatible = "snps,designware-i2c";
154 clock-frequency = <I2C_BITRATE_STANDARD>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 vendor-id = <0x8006>;
158 device-id = <0x5ab2>;
160 interrupt-parent = <&intc>;
166 compatible = "snps,designware-i2c";
167 clock-frequency = <I2C_BITRATE_STANDARD>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170 vendor-id = <0x8086>;
171 device-id = <0x5ab4>;
173 interrupt-parent = <&intc>;
179 compatible = "snps,designware-i2c";
180 clock-frequency = <I2C_BITRATE_STANDARD>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 vendor-id = <0x8086>;
184 device-id = <0x5ab6>;
186 interrupt-parent = <&intc>;
192 compatible = "snps,designware-i2c";
193 clock-frequency = <I2C_BITRATE_STANDARD>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 vendor-id = <0x8086>;
197 device-id = <0x5ab8>;
199 interrupt-parent = <&intc>;
205 compatible = "snps,designware-i2c";
206 clock-frequency = <I2C_BITRATE_STANDARD>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 vendor-id = <0x8086>;
210 device-id = <0x5aba>;
212 interrupt-parent = <&intc>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 compatible = "simple-bus";
225 compatible = "intel,vt-d";
236 interrupt-parent = <&intc>;
238 gpio-controller;
239 #gpio-cells = <2>;
242 pin-offset = <0>;
251 interrupt-parent = <&intc>;
253 gpio-controller;
254 #gpio-cells = <2>;
257 pin-offset = <32>;
266 interrupt-parent = <&intc>;
268 gpio-controller;
269 #gpio-cells = <2>;
272 pin-offset = <64>;
281 interrupt-parent = <&intc>;
283 gpio-controller;
284 #gpio-cells = <2>;
287 pin-offset = <0>;
296 interrupt-parent = <&intc>;
298 gpio-controller;
299 #gpio-cells = <2>;
302 pin-offset = <32>;
311 interrupt-parent = <&intc>;
313 gpio-controller;
314 #gpio-cells = <2>;
317 pin-offset = <64>;
326 interrupt-parent = <&intc>;
328 gpio-controller;
329 #gpio-cells = <2>;
332 pin-offset = <0>;
341 interrupt-parent = <&intc>;
343 gpio-controller;
344 #gpio-cells = <2>;
347 pin-offset = <32>;
356 interrupt-parent = <&intc>;
358 gpio-controller;
359 #gpio-cells = <2>;
362 pin-offset = <0>;
372 interrupt-parent = <&intc>;
374 gpio-controller;
375 #gpio-cells = <2>;
378 pin-offset = <32>;
387 interrupt-parent = <&intc>;
396 interrupt-parent = <&intc>;
397 alarms-count = <1>;
403 gpio_n: gpio-north {
405 compatible = "intel,apollo-lake-gpio";
406 #gpio-cells = <2>;
407 gpio-map-mask = <0xffffffff 0xffffffc0>;
408 gpio-map-pass-thru = <0 0x3f>;
409 gpio-map =
490 gpio_nw: gpio-northwest {
492 compatible = "intel,apollo-lake-gpio";
493 #gpio-cells = <2>;
494 gpio-map-mask = <0xffffffff 0xffffffc0>;
495 gpio-map-pass-thru = <0 0x3f>;
496 gpio-map =
576 gpio_w: gpio-west {
578 compatible = "intel,apollo-lake-gpio";
579 #gpio-cells = <2>;
580 gpio-map-mask = <0xffffffff 0xffffffc0>;
581 gpio-map-pass-thru = <0 0x3f>;
582 gpio-map =
632 gpio_sw: gpio-southwest {
634 compatible = "intel,apollo-lake-gpio";
635 #gpio-cells = <2>;
636 gpio-map-mask = <0xffffffff 0xffffffc0>;
637 gpio-map-pass-thru = <0 0x3f>;
638 gpio-map =