Lines Matching +full:reg +full:- +full:names
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <DT_FREQ_K(125125)>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 reg = <0>;
41 hlic0: interrupt-controller {
42 compatible = "riscv,cpu-intc";
43 #address-cells = <0>;
44 #interrupt-cells = <1>;
45 interrupt-controller;
51 mmu-type = "riscv,sv39";
52 reg = <0x1>;
55 hlic1: interrupt-controller {
56 compatible = "riscv,cpu-intc";
57 #address-cells = <0>;
58 #interrupt-cells = <1>;
59 interrupt-controller;
65 mmu-type = "riscv,sv39";
66 reg = <0x2>;
69 hlic2: interrupt-controller {
70 compatible = "riscv,cpu-intc";
71 #address-cells = <0>;
72 #interrupt-cells = <1>;
73 interrupt-controller;
79 mmu-type = "riscv,sv39";
80 reg = <0x3>;
83 hlic3: interrupt-controller {
84 compatible = "riscv,cpu-intc";
85 #address-cells = <0>;
86 #interrupt-cells = <1>;
87 interrupt-controller;
93 mmu-type = "riscv,sv39";
94 reg = <0x4>;
97 hlic4: interrupt-controller {
98 compatible = "riscv,cpu-intc";
99 #address-cells = <0>;
100 #interrupt-cells = <1>;
101 interrupt-controller;
107 #address-cells = <2>;
108 #size-cells = <2>;
109 compatible = "fu740-soc", "sifive-soc", "simple-bus";
114 reg = <0x0 0x1000 0x0 0x1000>;
115 reg-names = "mem";
120 reg = <0x0 0x10000 0x0 0x8000>;
121 reg-names = "mem";
126 reg = <0x0 0x1000000 0x0 0x2000>;
127 reg-names = "mem";
132 interrupts-extended = <&hlic0 3 &hlic0 7
137 reg = <0x0 0x2000000 0x0 0x10000>;
142 reg = <0x0 0x8000000 0x0 0x200000>;
143 reg-names = "mem";
147 plic: interrupt-controller@c000000 {
148 compatible = "sifive,plic-1.0.0";
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
152 interrupts-extended = <&hlic0 11
157 reg = <0x0 0x0c000000 0x0 0x04000000>;
158 riscv,max-priority = <7>;
164 interrupt-parent = <&plic>;
166 reg = <0x0 0x10010000 0x0 0x1000>;
167 reg-names = "control";
173 interrupt-parent = <&plic>;
175 reg = <0x0 0x10011000 0x0 0x1000>;
176 reg-names = "control";
182 interrupt-parent = <&plic>;
184 reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
185 reg-names = "control", "mem";
187 #address-cells = <1>;
188 #size-cells = <0>;
193 interrupt-parent = <&plic>;
195 reg = <0x0 0x10041000 0x0 0x1000>;
196 reg-names = "control";
198 #address-cells = <1>;
199 #size-cells = <0>;
204 interrupt-parent = <&plic>;
206 reg = <0x0 0x10050000 0x0 0x1000>;
207 reg-names = "control";
209 #address-cells = <1>;
210 #size-cells = <0>;
213 compatible = "sifive,fu740-c000-ddr";
214 reg = <0x0 0x100b0000 0x0 0x0800