Lines Matching +full:reg +full:- +full:names
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 tlclk: tl-clk {
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <2>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 i-cache-line-size = <0x4000>;
39 reg = <0x0>;
41 hlic0: interrupt-controller {
42 compatible = "riscv,cpu-intc";
43 #address-cells = <0>;
44 #interrupt-cells = <1>;
45 interrupt-controller;
52 mmu-type = "riscv,sv39";
53 i-cache-line-size = <0x8000>;
54 d-cache-line-size = <0x8000>;
55 reg = <0x1>;
57 hlic1: interrupt-controller {
58 compatible = "riscv,cpu-intc";
59 #address-cells = <0>;
60 #interrupt-cells = <1>;
61 interrupt-controller;
66 clock-frequency = <0>;
69 mmu-type = "riscv,sv39";
70 i-cache-line-size = <0x8000>;
71 d-cache-line-size = <0x8000>;
72 reg = <0x2>;
74 hlic2: interrupt-controller {
75 compatible = "riscv,cpu-intc";
76 #address-cells = <0>;
77 #interrupt-cells = <1>;
78 interrupt-controller;
83 clock-frequency = <0>;
86 mmu-type = "riscv,sv39";
87 i-cache-line-size = <0x8000>;
88 d-cache-line-size = <0x8000>;
89 reg = <0x3>;
91 hlic3: interrupt-controller {
92 compatible = "riscv,cpu-intc";
93 #address-cells = <0>;
94 #interrupt-cells = <1>;
95 interrupt-controller;
100 clock-frequency = <0>;
103 mmu-type = "riscv,sv39";
104 i-cache-line-size = <0x8000>;
105 d-cache-line-size = <0x8000>;
106 reg = <0x4>;
108 hlic4: interrupt-controller {
109 compatible = "riscv,cpu-intc";
110 #address-cells = <0>;
111 #interrupt-cells = <1>;
112 interrupt-controller;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fu540-soc", "sifive-soc", "simple-bus";
125 reg = <0x1000 0x1000>;
126 reg-names = "mem";
131 reg = <0x10000 0x8000>;
132 reg-names = "mem";
137 reg = <0x1000000 0x2000>;
138 reg-names = "mem";
143 reg = <0x1800000 0x2000>;
144 reg-names = "mem";
149 reg = <0x1808000 0x7000>;
150 reg-names = "mem";
155 reg = <0x1810000 0x7000>;
156 reg-names = "mem";
161 reg = <0x1818000 0x7000>;
162 reg-names = "mem";
167 reg = <0x1820000 0x7000>;
168 reg-names = "mem";
174 interrupts-extended = <&hlic0 3 &hlic0 7
179 interrupt-names = "soft0", "timer0", "soft1", "timer1",
182 reg = <0x2000000 0x10000>;
187 reg = <0x8000000 0x2000000>;
188 reg-names = "mem";
191 plic: interrupt-controller@c000000 {
192 compatible = "sifive,plic-1.0.0";
193 #interrupt-cells = <2>;
194 #address-cells = <1>;
195 interrupt-controller;
196 interrupts-extended = <&hlic0 11
201 reg = <0x0c000000 0x04000000>;
202 riscv,max-priority = <7>;
208 interrupt-parent = <&plic>;
210 reg = <0x10010000 0x1000>;
211 reg-names = "control";
217 interrupt-parent = <&plic>;
219 reg = <0x10011000 0x1000>;
220 reg-names = "control";
226 interrupt-parent = <&plic>;
228 reg = <0x10040000 0x1000 0x20000000 0x10000000>;
229 reg-names = "control", "mem";
231 #address-cells = <1>;
232 #size-cells = <0>;
237 interrupt-parent = <&plic>;
239 reg = <0x10041000 0x1000>;
240 reg-names = "control";
242 #address-cells = <1>;
243 #size-cells = <0>;
248 interrupt-parent = <&plic>;
250 reg = <0x10050000 0x1000>;
251 reg-names = "control";
253 #address-cells = <1>;
254 #size-cells = <0>;
259 gpio-controller;
261 interrupt-parent = <&plic>;
266 reg = <0x10060000 0x1000>;
267 reg-names = "control";
269 #gpio-cells = <2>;
271 #address-cells = <1>;
272 #size-cells = <1>;