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1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/gpio/gpio.h>
4 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
11 model = "SiFive,FE310G-0002-Z0";
13 coreclk: core-clk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <DT_FREQ_M(16)>;
19 tlclk: tl-clk {
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-div = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
35 hlic: interrupt-controller {
36 compatible = "riscv,cpu-intc";
37 #address-cells = <0>;
38 #interrupt-cells = <1>;
39 interrupt-controller;
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "sifive,FE310G-0002-Z0-soc", "fe310-soc",
47 "sifive-soc", "simple-bus";
51 interrupt-parent = <&plic>;
52 interrupts = <1 1>;
54 reg-names = "control";
58 interrupt-parent = <&plic>;
59 interrupts = <2 1>;
61 reg-names = "control";
65 interrupts-extended = <&hlic 3 &hlic 7>;
69 compatible = "riscv,machine-timer";
70 interrupts-extended = <&hlic 7>;
72 reg-names = "mtime", "mtimecmp";
74 debug: debug-controller@0 {
75 compatible = "sifive,debug-013", "riscv,debug-013";
76 interrupts-extended = <&hlic 65535>;
78 reg-names = "control";
83 reg-names = "mem";
85 error-device@3000 {
88 reg-names = "mem";
92 gpio-controller;
93 interrupt-parent = <&plic>;
94 interrupts = <8 1>, <9 1>, <10 1>, <11 1>,
95 <12 1>, <13 1>, <14 1>, <15 1>,
96 <16 1>, <17 1>, <18 1>, <19 1>,
97 <20 1>, <21 1>, <22 1>, <23 1>,
98 <24 1>, <25 1>, <26 1>, <27 1>,
99 <28 1>, <29 1>, <30 1>, <31 1>,
100 <32 1>, <33 1>, <34 1>, <35 1>,
101 <36 1>, <37 1>, <38 1>, <39 1>;
103 reg-names = "control";
105 #gpio-cells = <2>;
107 #address-cells = <1>;
108 #size-cells = <1>;
118 interrupt-parent = <&plic>;
119 interrupts = <52 1>;
121 reg-names = "control";
123 #address-cells = <1>;
124 #size-cells = <0>;
126 plic: interrupt-controller@c000000 {
127 compatible = "sifive,plic-1.0.0";
128 #address-cells = <0>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 interrupts-extended = <&hlic 11>;
133 riscv,max-priority = <7>;
139 reg-names = "mem";
144 reg-names = "control", "mem";
149 reg-names = "control";
153 interrupt-parent = <&plic>;
154 interrupts = <40 1>, <41 1>, <42 1>, <43 1>;
156 reg-names = "control";
158 sifive,compare-width = <8>;
159 #pwm-cells = <2>;
163 interrupt-parent = <&plic>;
164 interrupts = <44 1>, <45 1>, <46 1>, <47 1>;
166 reg-names = "control";
168 sifive,compare-width = <16>;
169 #pwm-cells = <2>;
173 interrupt-parent = <&plic>;
174 interrupts = <48 1>, <49 1>, <50 1>, <51 1>;
176 reg-names = "control";
178 sifive,compare-width = <16>;
179 #pwm-cells = <2>;
184 reg-names = "mem";
189 reg-names = "mem";
193 interrupt-parent = <&plic>;
194 interrupts = <3 1>;
196 reg-names = "control";
201 interrupt-parent = <&plic>;
202 interrupts = <4 1>;
204 reg-names = "control";
209 interrupt-parent = <&plic>;
210 interrupts = <5 1>;
212 reg-names = "control", "mem";
214 #address-cells = <1>;
215 #size-cells = <0>;
219 interrupt-parent = <&plic>;
220 interrupts = <6 1>;
222 reg-names = "control";
224 #address-cells = <1>;
225 #size-cells = <0>;
229 interrupt-parent = <&plic>;
230 interrupts = <7 1>;
232 reg-names = "control";
234 #address-cells = <1>;
235 #size-cells = <0>;
240 reg-names = "control";