Lines Matching +full:0 +full:- +full:1
1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/gpio/gpio.h>
4 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "sifive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
11 model = "SiFive,FE310G-0002-Z0";
13 coreclk: core-clk {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <DT_FREQ_M(16)>;
19 tlclk: tl-clk {
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-div = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu: cpu@0 {
32 reg = <0>;
35 hlic: interrupt-controller {
36 compatible = "riscv,cpu-intc";
37 #address-cells = <0>;
38 #interrupt-cells = <1>;
39 interrupt-controller;
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "sifive,FE310G-0002-Z0-soc", "fe310-soc",
47 "sifive-soc", "simple-bus";
51 interrupt-parent = <&plic>;
52 interrupts = <1 1>;
53 reg = <0x10000000 0x40>;
54 reg-names = "control";
58 interrupt-parent = <&plic>;
59 interrupts = <2 1>;
60 reg = <0x10000040 0x9c0>;
61 reg-names = "control";
65 interrupts-extended = <&hlic 3 &hlic 7>;
66 reg = <0x2000000 0x10000>;
68 debug: debug-controller@0 {
69 compatible = "sifive,debug-013", "riscv,debug-013";
70 interrupts-extended = <&hlic 65535>;
71 reg = <0x0 0x1000>;
72 reg-names = "control";
76 reg = <0x80000000 0x4000>;
77 reg-names = "mem";
79 error-device@3000 {
81 reg = <0x3000 0x1000>;
82 reg-names = "mem";
86 gpio-controller;
87 interrupt-parent = <&plic>;
88 interrupts = <8 1>, <9 1>, <10 1>, <11 1>,
89 <12 1>, <13 1>, <14 1>, <15 1>,
90 <16 1>, <17 1>, <18 1>, <19 1>,
91 <20 1>, <21 1>, <22 1>, <23 1>,
92 <24 1>, <25 1>, <26 1>, <27 1>,
93 <28 1>, <29 1>, <30 1>, <31 1>,
94 <32 1>, <33 1>, <34 1>, <35 1>,
95 <36 1>, <37 1>, <38 1>, <39 1>;
96 reg = <0x10012000 0x1000>;
97 reg-names = "control";
99 #gpio-cells = <2>;
101 #address-cells = <1>;
102 #size-cells = <1>;
107 reg = <0x10012038 0x8>;
112 interrupt-parent = <&plic>;
113 interrupts = <52 1>;
114 reg = <0x10016000 0x1000>;
115 reg-names = "control";
117 #address-cells = <1>;
118 #size-cells = <0>;
120 plic: interrupt-controller@c000000 {
121 compatible = "sifive,plic-1.0.0";
122 #address-cells = <0>;
123 #interrupt-cells = <2>;
124 interrupt-controller;
125 interrupts-extended = <&hlic 11>;
126 reg = <0x0c000000 0x04000000>;
127 riscv,max-priority = <7>;
132 reg = <0x8000000 0x2000>;
133 reg-names = "mem";
137 reg = <0x10010000 0x1000 0x20000 0x2000>;
138 reg-names = "control", "mem";
142 reg = <0x10008000 0x1000>;
143 reg-names = "control";
147 interrupt-parent = <&plic>;
148 interrupts = <40 1>, <41 1>, <42 1>, <43 1>;
149 reg = <0x10015000 0x1000>;
150 reg-names = "control";
152 sifive,compare-width = <8>;
153 #pwm-cells = <2>;
157 interrupt-parent = <&plic>;
158 interrupts = <44 1>, <45 1>, <46 1>, <47 1>;
159 reg = <0x10025000 0x1000>;
160 reg-names = "control";
162 sifive,compare-width = <16>;
163 #pwm-cells = <2>;
167 interrupt-parent = <&plic>;
168 interrupts = <48 1>, <49 1>, <50 1>, <51 1>;
169 reg = <0x10035000 0x1000>;
170 reg-names = "control";
172 sifive,compare-width = <16>;
173 #pwm-cells = <2>;
177 reg = <0x1000 0x1000>;
178 reg-names = "mem";
182 reg = <0x10000 0x2000>;
183 reg-names = "mem";
187 interrupt-parent = <&plic>;
188 interrupts = <3 1>;
189 reg = <0x10013000 0x1000>;
190 reg-names = "control";
195 interrupt-parent = <&plic>;
196 interrupts = <4 1>;
197 reg = <0x10023000 0x1000>;
198 reg-names = "control";
203 interrupt-parent = <&plic>;
204 interrupts = <5 1>;
205 reg = <0x10014000 0x1000 0x20000000 0x20000000>;
206 reg-names = "control", "mem";
208 #address-cells = <1>;
209 #size-cells = <0>;
213 interrupt-parent = <&plic>;
214 interrupts = <6 1>;
215 reg = <0x10024000 0x1000>;
216 reg-names = "control";
218 #address-cells = <1>;
219 #size-cells = <0>;
223 interrupt-parent = <&plic>;
224 interrupts = <7 1>;
225 reg = <0x10034000 0x1000>;
226 reg-names = "control";
228 #address-cells = <1>;
229 #size-cells = <0>;
233 reg = <0x4000 0x1000>;
234 reg-names = "control";