Lines Matching +full:0 +full:x01
29 #size-cells = <0>;
30 cpu0: cpu@0 {
34 reg = <0>;
57 reg = <0x00f02200 0xc0>;
61 reg = <0x00f01000 0x100>;
67 reg = <0x80000000 DT_SIZE_M(1)>;
75 reg = <0x80100000 DT_SIZE_K(60)>;
79 reg = <0xf01040 3 /* SCAR0 */
80 0xf01043 3
81 0xf01046 3
82 0xf01049 3
83 0xf0104c 3 /* SCAR4 */
84 0xf01081 3 /* SCAR5 */
85 0xf01084 3
86 0xf01087 3
87 0xf0108a 3
88 0xf0108d 3
89 0xf01090 3
90 0xf01093 3
91 0xf01096 3 /* SCAR12 */
92 0xf010b0 3 /* SCAR13 */
93 0xf010b3 3
94 0xf010b6 3
95 0xf010b9 3
96 0xf010bc 3
97 0xf010bf 3
98 0xf010c2 3
99 0xf010c5 3
100 0xf010c8 3
101 0xf010cb 3
102 0xf010ce 3>; /* SCAR23 */
107 reg = <0x00f02700 0x0020>;
113 reg-shift = <0>;
117 reg = <0x00f02800 0x0020>;
123 reg-shift = <0>;
128 reg = <0x00f02720 0x0020>;
131 gpios = <&gpiob 0 0>;
137 reg = <0x00f02820 0x0020>;
140 gpios = <&gpioh 1 0>;
146 reg = <0x00f01f10 0x0052>;
158 reg = <0x00f01601 1 /* GPDR (set) */
159 0x00f01610 8 /* GPCR */
160 0x00f01661 1 /* GPDMR (get) */
161 0x00f01671 1>; /* GPOTR */
178 reg = <0x00f01602 1 /* GPDR (set) */
179 0x00f01618 8 /* GPCR */
180 0x00f01662 1 /* GPDMR (get) */
181 0x00f01672 1>; /* GPOTR */
199 reg = <0x00f01603 1 /* GPDR (set) */
200 0x00f01620 8 /* GPCR */
201 0x00f01663 1 /* GPDMR (get) */
202 0x00f01673 1>; /* GPOTR */
219 reg = <0x00f01604 1 /* GPDR (set) */
220 0x00f01628 8 /* GPCR */
221 0x00f01664 1 /* GPDMR (get) */
222 0x00f01674 1>; /* GPOTR */
239 reg = <0x00f01605 1 /* GPDR (set) */
240 0x00f01630 8 /* GPCR */
241 0x00f01665 1 /* GPDMR (get) */
242 0x00f01675 1>; /* GPOTR */
259 reg = <0x00f01606 1 /* GPDR (set) */
260 0x00f01638 8 /* GPCR */
261 0x00f01666 1 /* GPDMR (get) */
262 0x00f01676 1>; /* GPOTR */
279 reg = <0x00f01607 1 /* GPDR (set) */
280 0x00f01640 8 /* GPCR */
281 0x00f01667 1 /* GPDMR (get) */
282 0x00f01677 1>; /* GPOTR */
299 reg = <0x00f01608 1 /* GPDR (set) */
300 0x00f01648 8 /* GPCR */
301 0x00f01668 1 /* GPDMR (get) */
302 0x00f01678 1>; /* GPOTR */
312 0 IRQ_TYPE_LEVEL_HIGH>;
320 reg = <0x00f01609 1 /* GPDR (set) */
321 0x00f01650 8 /* GPCR */
322 0x00f01669 1 /* GPDMR (get) */
323 0x00f01679 1>; /* GPOTR */
340 reg = <0x00f0160a 1 /* GPDR (set) */
341 0x00f01658 8 /* GPCR */
342 0x00f0166a 1 /* GPDMR (get) */
343 0x00f0167a 1>; /* GPOTR */
360 reg = <0x00f0160b 1 /* GPDR (set) */
361 0x00f01690 8 /* GPCR */
362 0x00f0166b 1 /* GPDMR (get) */
363 0x00f0167b 1>; /* GPOTR */
380 reg = <0x00f0160c 1 /* GPDR (set) */
381 0x00f01698 8 /* GPCR */
382 0x00f0166c 1 /* GPDMR (get) */
383 0x00f0167c 1>; /* GPOTR */
400 reg = <0x00f0160d 1 /* GPDR (set) */
401 0x00f016a0 8 /* GPCR */
402 0x00f0166d 1 /* GPDMR (get) */
403 0x00f0167d 1>; /* GPOTR */
413 0 IRQ_TYPE_LEVEL_HIGH>;
420 reg = <0x00f03100 0xd8 /* eSPI slave */
421 0x00f03200 0x9a /* eSPI VW */
422 0x00f03300 0xd0 /* eSPI Queue 0 */
423 0x00f03400 0xc0 /* eSPI Queue 1 */
424 0x00f01200 6 /* EC2I bridge */
425 0x00f01300 11 /* Host KBC */
426 0x00f01500 0x100 /* Host PMC */
427 0x00f01000 0xd1>; /* SMFI */
445 reg = <0x00f03a00 0x30>;
446 interrupts = <171 0>;
454 reg = <0xf01900 0x45>;
462 reg = <0xf01946 0x01 /* VCMP0CTL */
463 0xf01977 0x01 /* VCMP0CSELM */
464 0xf01937 0x01 /* VCMPSCP */
465 0xf01947 0x01 /* VCMP0THRDATM */
466 0xf01948 0x01 /* VCMP0THRDATL */
467 0xf01945 0x01 /* VCMPSTS */
468 0xf0196d 0x01>; /* VCMPSTS2 */
476 reg = <0xf01949 0x01 /* VCMP1CTL */
477 0xf01978 0x01 /* VCMP1CSELM */
478 0xf01937 0x01 /* VCMPSCP */
479 0xf0194a 0x01 /* VCMP1THRDATM */
480 0xf0194b 0x01 /* VCMP1THRDATL */
481 0xf01945 0x01 /* VCMPSTS */
482 0xf0196d 0x01>; /* VCMPSTS2 */
490 reg = <0xf0194c 0x01 /* VCMP2CTL */
491 0xf01979 0x01 /* VCMP2CSELM */
492 0xf01937 0x01 /* VCMPSCP */
493 0xf0194d 0x01 /* VCMP2THRDATM */
494 0xf0194e 0x01 /* VCMP2THRDATL */
495 0xf01945 0x01 /* VCMPSTS */
496 0xf0196d 0x01>; /* VCMPSTS2 */
504 reg = <0xf0196e 0x01 /* VCMP3CTL */
505 0xf0197a 0x01 /* VCMP3CSELM */
506 0xf01937 0x01 /* VCMPSCP */
507 0xf0196f 0x01 /* VCMP3THRDATM */
508 0xf01970 0x01 /* VCMP3THRDATL */
509 0xf01945 0x01 /* VCMPSTS */
510 0xf0196d 0x01>; /* VCMPSTS2 */
518 reg = <0xf01971 0x01 /* VCMP4CTL */
519 0xf0197b 0x01 /* VCMP4CSELM */
520 0xf01937 0x01 /* VCMPSCP */
521 0xf01972 0x01 /* VCMP4THRDATM */
522 0xf01973 0x01 /* VCMP4THRDATL */
523 0xf01945 0x01 /* VCMPSTS */
524 0xf0196d 0x01>; /* VCMPSTS2 */
532 reg = <0xf01974 0x01 /* VCMP5CTL */
533 0xf0197c 0x01 /* VCMP5CSELM */
534 0xf01937 0x01 /* VCMPSCP */
535 0xf01975 0x01 /* VCMP5THRDATM */
536 0xf01976 0x01 /* VCMP5THRDATL */
537 0xf01945 0x01 /* VCMPSTS */
538 0xf0196d 0x01>; /* VCMPSTS2 */
547 reg = <0x00f01e00 0x11>;
552 reg = <0x00f01800 1>;
556 reg = <0x00f01802 1 /* DCR */
557 0x00f0180c 1 /* PCSSG */
558 0x00f0180f 1 /* PCSG */
559 0x00f0180a 1>; /* PWMPOL */
567 reg = <0x00f01803 1 /* DCR */
568 0x00f0180c 1 /* PCSSG */
569 0x00f0180f 1 /* PCSG */
570 0x00f0180a 1>; /* PWMPOL */
578 reg = <0x00f01804 1 /* DCR */
579 0x00f0180c 1 /* PCSSG */
580 0x00f0180f 1 /* PCSG */
581 0x00f0180a 1>; /* PWMPOL */
589 reg = <0x00f01805 1 /* DCR */
590 0x00f0180c 1 /* PCSSG */
591 0x00f0180f 1 /* PCSG */
592 0x00f0180a 1>; /* PWMPOL */
600 reg = <0x00f01806 1 /* DCR */
601 0x00f0180d 1 /* PCSSG */
602 0x00f0180f 1 /* PCSG */
603 0x00f0180a 1>; /* PWMPOL */
611 reg = <0x00f01807 1 /* DCR */
612 0x00f0180d 1 /* PCSSG */
613 0x00f0180f 1 /* PCSG */
614 0x00f0180a 1>; /* PWMPOL */
622 reg = <0x00f01808 1 /* DCR */
623 0x00f0180d 1 /* PCSSG */
624 0x00f0180f 1 /* PCSG */
625 0x00f0180a 1>; /* PWMPOL */
633 reg = <0x00f01809 1 /* DCR */
634 0x00f0180d 1 /* PCSSG */
635 0x00f0180f 1 /* PCSG */
636 0x00f0180a 1>; /* PWMPOL */
644 reg = <0x00f0181e 1 /* F1TLRR */
645 0x00f0181f 1 /* F1TMRR */
646 0x00f01848 1>; /* TSWCTLR */
653 reg = <0x00f01820 1 /* F2TLRR */
654 0x00f01821 1 /* F2TMRR */
655 0x00f01848 1>; /* TSWCTLR */
657 chsel-bit = <BIT(0)>;
663 reg = <0x00f02000 0x100>;
668 reg = <0x00f02c00 15>;
670 #size-cells = <0>;
678 reg = <0x00f01d00 0x29>;
682 wucctrl = <&wuc_wu30 /* KSI[0] */
696 reg = <0x00f03700 0x100>;
702 reg = <0x00f03800 0x100>;