Lines Matching full:delay

37   spi-sck-cs-delay:
40       A delay in nanoseconds between the stop of clock signal and
42       asserted between transfer, this delay will be inserted between transfer.
43       If not set, the minimum supported delay is used.
47   spi-cs-sck-delay:
50       A delay in nanoseconds between activating Chip Select and the start
52       between transfer, this delay will be inserted between transfer.
53       If not set, the minimum supported delay is used.
57   spi-cs-cs-delay:
60       A delay in nanoseconds between deactivating Chip Select at the stop
62       next transfer. If CS remains asserted between transfer, this delay
64       If not set, the minimum supported delay is used.