Lines Matching full:delay

11   pre-delay:
14       Delay in nanoseconds inserted between chip select assert to the first
15       clock edge. If not set, no additional delay is inserted.
17   post-delay:
20       Delay in nanoseconds inserted between the last clock edge to the chip
21       select deassert. If not set, no additional delay is inserted.
23   frame-delay:
26       Delay in nanoseconds inserted between data frames when chip select is
27       asserted and the EOF flag is set. If not set, no additional delay is
30   transfer-delay:
33       Delay in nanoseconds inserted between transfers when chip select is
34       deasserted. If not set, no additional delay is inserted.