Lines Matching +full:tx +full:- +full:channel

3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11   input-src:
20       - "DX0A"
21       - "DX0B"
22       - "DX0C"
23       - "DX0D"
24       - "DX0E"
25       - "DX0F"
26       - "DX0G"
28   pinctrl-0:
31   pinctrl-names:
34   fifo-start-offset:
38       where the tx and rx fifos will start. When sharing the fifo, the user must properly
39       define the offset based on the configuration of the other channel. The fifo has a
40       capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned
46   fifo-tx-size:
50       then fifo-tx-size should be set to 0.
54       - 0
55       - 2
56       - 4
57       - 8
58       - 16
59       - 32
60       - 64
62   fifo-rx-size:
66       then fifo-rx-size should be set to 0.
70       - 0
71       - 2
72       - 4
73       - 8
74       - 16
75       - 32
76       - 64
88       Optional TX & RX dma specifiers used by async UART.
92       where the first entry is for the TX, and the second for RX.
94       The parameters in the dma entry are: dma device phandle, dma channel, dma priority (0 is
98       1. Select a dma device and a free dma channel.
102          simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
103          In USIC1, interrupt 90->SR0, 91->SR1, etc.
107       For example, say we select interrupt 85 on USIC0, dma0, channel 3, priority 4, and line 7.
112   dma-names:
114       Required if the dmas property exists. Should be set to "tx" and "rx"
118          dma-names = "tx", "rx";