Lines Matching +full:dma +full:- +full:offset

3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11   input-src:
20       - "DX0A"
21       - "DX0B"
22       - "DX0C"
23       - "DX0D"
24       - "DX0E"
25       - "DX0F"
26       - "DX0G"
28   pinctrl-0:
31   pinctrl-names:
34   fifo-start-offset:
37       usic0ch0 and usic0ch1 will share the same fifo. This parameter defines an offset
39       define the offset based on the configuration of the other channel. The fifo has a
40       capacity of 64 entries. The tx/rx fifos are created on fifo-xx-size aligned
46   fifo-tx-size:
50       then fifo-tx-size should be set to 0.
54       - 0
55       - 2
56       - 4
57       - 8
58       - 16
59       - 32
60       - 64
62   fifo-rx-size:
66       then fifo-rx-size should be set to 0.
70       - 0
71       - 2
72       - 4
73       - 8
74       - 16
75       - 32
76       - 64
88       Optional TX & RX dma specifiers used by async UART.
94       The parameters in the dma entry are: dma device phandle, dma channel, dma priority (0 is
95       lowest and 7 is highest), and an opaque entry for the dma line routing parameters set
98       1. Select a dma device and a free dma channel.
99       1. Select a free dma line. dma0 device can only connect to lines [0, 7] and
102          simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
103          In USIC1, interrupt 90->SR0, 91->SR1, etc.
104       3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
108       The interrupt would map to SR1. From Table "DMA Request Source Selection", request_source
110       dma = <&dma0 3 4 XMC4XXX_SET_CONFIG(7,10) ... >;
112   dma-names:
118          dma-names = "tx", "rx";