Lines Matching +full:one +full:- +full:timer +full:- +full:only

1 description: Xilinx AXI Timer IP node
3 compatible: "xlnx,xps-timer-1.00.a"
8 # https://github.com/Xilinx/meta-xilinx
11   clock-frequency:
14   xlnx,count-width:
18       - 8
19       - 16
20       - 32
22       Individual timer/counter width in bits.
24   xlnx,gen0-assert:
27       - 0
28       - 1
30       Active state of the generateout0 signal (0 for active-low, 1 for
31       active-high).
33   xlnx,gen1-assert:
36       - 0
37       - 1
39       Active state of the generateout1 signal (0 for active-low, 1 for
40       active-high).
42   xlnx,one-timer-only:
46       - 0
47       - 1
49       0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled.
51   xlnx,trig0-assert:
54       - 0
55       - 1
57       Active state of the capturetrig0 signal (0 for active-low, 1 for
58       active-high).
60   xlnx,trig1-assert:
63       - 0
64       - 1
66       Active state of the capturetrig1 signal (0 for active-low, 1 for
67       active-high).