Lines Matching full:timer

17   and asymmetric configuration. MCPWMxA and MCPWMxB will share the same timer, thus having the same
20   The driver currently always use the timer x for operator x. Timer 0 will use operator 0 for
22   Timer 1 will use operator 1 for PWM1A/B, and so on.
25   Channel 0 -> Timer 0, Operator 0, output PWM0A
26   Channel 1 -> Timer 0, Operator 0, output PWM0B
27   Channel 2 -> Timer 1, Operator 1, output PWM1A
28   Channel 3 -> Timer 1, Operator 1, output PWM1B
29   Channel 4 -> Timer 2, Operator 2, output PWM2A
30   Channel 5 -> Timer 2, Operator 2, output PWM2B
89       8 bit timer prescale for the global clock.
98       8 bit timer prescale for timer 0.
104       8 bit timer prescale for timer 1.
110       8 bit timer prescale for timer 2.