Lines Matching +full:phys +full:- +full:clock

2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-mipi-dsi"
8 include: [mipi-dsi-host.yaml]
17   interrupt-names:
18     type: string-array
22   pll-div:
28   pll-mul-int:
33   pll-mul-frac:
39   lp-divisor:
44   ulps-wakeup-period:
48   video-mode-delay:
58 child-binding:
60     MIPI PHY timing configuration. The child node must be named "phys-timing".
61     Refer to '57. MIPI PHY - RA8D1 MCU group HWM' for detail parameter description.
64     t-init:
68         Minimum duration of the TINIT state (Units: operation clock cycles).
70     t-clk-prep:
74         Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state).
76     t-hs-prep:
80         Duration of the data lane LP-00 state (immediately before entry to the HS-0 state).
82     t-lp-exit:
86         Low-power transition time to High-Speed mode.
92         Clock lane pre and post data timing parameter: <TCLKZERO TCLKPRE TCLKPOST TCLKTRL>
98         High-Speed data lane timing parameter: <THSZERO THSTRL THSEXIT>