Lines Matching full:cycles

112       expressed in number of memory clock cycles. It must be set at least to
113       41 SDRAM clock cycles.
133         - CAS: SDRAM CAS latency in number of memory clock cycles.
138         - RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
149           Refresh command in number of memory clock cycles.
151           Activate command in number of memory clock cycles. If two SDRAM
154         - TRAS: Minimum Self-refresh period in number of memory clock cycles.
157           expressed in number of memory clock cycles. If two SDRAM devices are
161           clock cycles
163           of memory clock cycles. If two SDRAM devices are used, the TRP must be
166           number of memory clock cycles.