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8 memories. Up to 2 SDRAM banks are supported with independent configuration. It
9 is worth to note that while settings are independent, some are shared or are
13 The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
73 respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
104 register bits are also used to program the extended mode register for
127 SDRAM control configuration. Expected fields, in order, are,
134 - SDCLK: SDRAM clock period. If two SDRAM devices are used both should
136 - RBURST: Enable burst read mode. If two SDRAM devices are used both
139 latency. If two SDRAM devices are used both should have the same
146 SDRAM timing configuration. Expected fields, in order, are,
152 devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with
157 expressed in number of memory clock cycles. If two SDRAM devices are
163 of memory clock cycles. If two SDRAM devices are used, the TRP must be