Lines Matching +full:2 +full:- +full:phase
2 # SPDX-License-Identifier: Apache-2.0
11 - 8 bits
12 - 16 bits
13 - 32 bits
15 - Asynchronous mode
16 - Burst mode for synchronous accesses with configurable option to split burst
18 - Multiplexed or non-multiplexed
20 - Asynchronous mode
21 - Burst mode for synchronous accesses
22 - Multiplexed or non-multiplexed
37 pinctrl-0 = <&fmc_nwe_pd5 &fmc_noe_pd4 ...>;
38 pinctrl-names = "default";
42 compatible = "st,stm32-fmc-nor-psram";
44 #address-cells = <1>;
45 #size-cells = <0>;
47 sram2@2 {
63 st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
68 Use constants defined in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
70 compatible: "st,stm32-fmc-nor-psram"
75 "#address-cells":
79 "#size-cells":
83 child-binding:
95 SRAM/NOR-Flash control register (FMC_BCRx).
102 * MUXEN - Address/data multiplexing enable bit.
103 * MTYP - Memory type.
104 * MWID - Memory data bus width.
105 * FACCEN - Flash access enable.
106 * BURSTEN - Burst enable bit.
107 * WAITPOL - Wait signal polarity bit.
108 * WAITCFG - Wait timing configuration.
109 * WREN - Write enable bit.
110 * WAITEN - Wait enable bit.
111 * EXTMOD - Extended mode enable.
112 If set, then 'st,timing-ext' shall be provided.
113 * ASYNCWAIT - Wait signal during asynchronous transfers.
114 * CPSIZE - Cellular RAM (CRAM) 1.5 Page Size.
115 * CBURSTRW - Write burst enable.
116 * CCLKEN - Continuous Clock Enable.
117 * WFDIS - Write FIFO Disable.
118 * BMAP - FMC bank mapping.
124 SRAM/NOR-Flash (read) timing register (FMC_BTRx).
129 'st,timing-ext' to configure write accesses.
133 * ADDSET - Address setup phase duration.
138 * ADDHLD - Address-hold phase duration.
143 * DATAST - Data-phase duration.
149 * BUSTURN - Bus turnaround phase duration.
154 * CLKDIV - Clock divide ratio (for FMC_CLK signal).
157 between Min_Data = 2 and Max_Data = 16.
160 * DATLAT - Data latency for synchronous memory.
164 - It must be set to 0 in case of a CRAM
165 - It is don't care in asynchronous NOR, SRAM or ROM accesses
166 - It may assume a value between Min_Data = 2 and Max_Data = 17
168 * ACCMOD - Access mode.
170 in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
172 st,timing-ext:
176 SRAM/NOR-Flash (write) timing register (FMC_BWTRx).
180 * ADDSET - Address setup phase duration.
182 * ADDHLD - Address-hold phase duration.
184 * DATAST - Data-phase duration.
186 * BUSTURN - Bus turnaround phase duration.
188 * ACCMOD - Access mode.