Lines Matching full:controller

5   NXP S32 GPIO controller.
7   The GPIO controller provides the option to route external input pad interrupts
8   to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9   the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10   SIUL2 EIRQ interrupt controller.
12   To route external interrupts to the WKPU interrupt controller, the GPIO
14   the following snippet of devicetree source code instructs the GPIO controller
15   to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
24   interrupt controller allows for the allocation of distinct interrupt
26   the fact that each interrupt controller features its own interrupt vector.
28   the interrupt controller configured with a lower priority compared to the one
34   as the interrupt controller for the corresponding GPIO. It's worth noting that
40 include: [gpio-controller.yaml, base.yaml]
58       NXP WKPU controller associated to this GPIO port.