Lines Matching full:be
24 frequency will be derived using two dividers in the respective GEM's
27 which it will be adjusted at run-time. Therefore, the value of this
28 item must be set to the clock frequency of the PLL supplying the
48 interval, link-speed and advertise-lower-link-speeds should be checked
57 PHY will be claimed by the driver, watch out in case of shared MDIO
72 the respective controller will be configured to match the link speed
74 the link speed specified here will be requested. If the optional pro-
77 be requested.
108 of memory accesses. This option CAN NOT be used if any component ex-
136 8 kB should be the default.
154 that are available. If unset, the hardware TX data buffer will be
161 The number of descriptors to be allocated in the RX buffer descriptor
162 ring. Must be <= 255.
168 The size of each receive data buffer, must be a multiple of 8, highest
175 The number of descriptors to be allocated in the TX buffer descriptor
176 ring. Must be <= 255.
196 non-standard preamble will not be rejected.
202 IPG can be increased above 96 bit times depending on the previous
217 When set, frames with FCS/CRC errors will not be rejected. FCS error
218 statistics will still be collected for frames with bad FCS and FCS
219 status will be recorded in the frame's DMA descriptor. This option
220 should not be activated for normal operation.
225 Optional feature flag - Enable frames to be received in half-duplex
232 hardware. Frames with bad IP, TCP or UDP checksums will be discarded.
250 nation address match is found the pause frame will be copied to
258 When set, received frames will be written to memory without their
260 be reduced by four bytes in this mode.
268 frame) will be discarded. This only applies to frames with a length
288 external address match interface can be used to copy frames to memory.
300 will be accepted when the 6 bit hash function of the destination
307 frames will be accepted when the 6 bit hash function of the desti-
314 addressed to the all-ones broadcast address will be rejected.
320 frames will be accepted.
325 only VLAN tagged frames will be passed to the address matching logic.
342 endian. If this flag is not set, data will be little endian.
348 ness swap to big endian. If this flag is not set, data will be little