Lines Matching +full:0 +full:x012a
35 -bit 0-1 : Direction (see dma.h)
36 0x0: MEM to MEM
37 0x1: MEM to PERIPH
38 0x2: PERIPH to MEM
39 0x3: reserved for PERIPH to PERIPH
41 0x0: no address increment between transfers
42 0x1: increment address between transfers
44 0x0: no address increment between transfers
45 0x1: increment address between transfers
47 0x0: Byte (8 bits)
48 0x1: Half-word (16 bits)
49 0x2: Word (32 bits)
50 0x3: Double word (64 bits)
51 0x4: Quad word (128 bits)
52 0x5: Eight word (256 bits)
53 0x6-0x7: reserved
55 0x0: Byte (8 bits)
56 0x1: Half-word (16 bits)
57 0x2: Word (32 bits)
58 0x3: Double word (64 bits)
59 0x4: Quad word (128 bits)
60 0x5: Eight word (256 bits)
61 0x6-0x7: reserved
63 0x0: lower priority
64 0x1: higher priority
77 Tx using channel 2, slot 0
81 dmas = <&dma0 2 0 0x0129>,
82 <&dma0 3 1 0x012A>;