Lines Matching full:of
13 description: Optional IRQ line of FT800 controller
27 Polarity of PCLK. If it is set to zero, PCLK polarity is on
35 Controls the transition of RGB signals with PCLK active clock
37 following the active edge of PCLK. When set to 1, R[7:2]
45 Controls the arrangement of output RGB pins, which may help
52 description: Number of visible lines of pixels in one frame
57 description: Number of invisible lines at the beginning of a new frame
63 Number of all lines in a frame. It includes all visible and
64 invisible lines at the beginning and at the end of a frame.
70 Number of lines for the high state of signal VSYNC at
71 the start of new frame.
77 Number of lines for signal VSYNC toggle takes at the start
78 of new frame.
83 description: Number of PCLK cycles per visible part of horizontal line
89 Number of PCLK cycles before pixels are scanned out for
95 description: Number of total PCLK cycles per horizontal line scan.
100 description: Number of PCLK cycles of HSYNC high state during start of
106 description: Number of PCLK cycles for HSYNC toggle during start of line.