Lines Matching +full:peripheral +full:- +full:in

2 # SPDX-License-Identifier: Apache-2.0
6   This node is in charge of system clock ('SYSCLK') source selection and controlling
7   clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
11   System clock source should be selected amongst the clock nodes available in "clocks"
13   Core clock frequency should also be defined, using "clock-frequency" property.
16   Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
21            ahb-prescaler = <2>;
22            clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23            apb1-presacler = <1>;
24            apb2-presacler = <1>;
25            apb7-presacler = <7>;
30   To specify a gated clock, a peripheral should define a "clocks" property encoded
31   in the following way:
38   the bus controlling the peripheral and the second index specifies the bit used to
39   control the peripheral clock in that bus register.
51   In this example I2C1 device is assigned HSI as clock source.
52   It is device driver's responsibility to query and use clock source information in
55 compatible: "st,stm32wba-rcc"
57 include: [clock-controller.yaml, base.yaml]
63   "#clock-cells":
66   clock-frequency:
70       default frequency in Hz for clock output (HCLK1)
72   ahb-prescaler:
76       - 1
77       - 2
78       - 4
79       - 8
80       - 16
86   ahb5-prescaler:
89       - 1
90       - 2
91       - 3
92       - 4
93       - 6
100   apb1-prescaler:
104       - 1
105       - 2
106       - 4
107       - 8
108       - 16
110   apb2-prescaler:
114       - 1
115       - 2
116       - 4
117       - 8
118       - 16
120   apb7-prescaler:
124       - 1
125       - 2
126       - 4
127       - 8
128       - 16
130   ahb5-div:
137 clock-cells:
138   - bus
139   - bits