Lines Matching full:pll
5 STM32WB and STM32WL PLL node.
7 It can be used to describe 2 different PLLs: PLL, PLLSAI1.
8 Only main PLL is supported for now.
14 Each PLL can have up to 3 output clocks and for each output clock, the
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
23 The PLL output frequency must not exceed:
27 compatible: "st,stm32wb-pll-clock"
42 Main PLL division factor for PLL input clock
49 Main PLL multiplication factor for VCO
55 Main PLL division factor for PLLPCLK
61 Main PLL division factor for PLLQCLK
68 Main PLL division factor for PLLRCLK (system clock)