Lines Matching +full:clock +full:- +full:frequency

2 # SPDX-License-Identifier: Apache-2.0
9   These PLLs can take one of clk_hse, clk_hsi or clk_msi as input clock, with
10   an input frequency from 5 to 50 MHz. PLLM factor is used to set the input
11   clock in this acceptable range.
13   Each PLL has one output clock whose frequency can be computed with the
16     f(PLL_P) = f(VCO clock) / (PLLP1 × PLLP2)
18       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
21         clock output to the lowest frequency.
23   The PLL output frequency must not exceed 3200 MHz.
25 compatible: "st,stm32n6-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
31   "#clock-cells":
37   div-m:
42         input clock
43         Valid range: 1 - 63
45   mul-n:
50         Valid range: 16 - 2500
52   div-p1:
56         Valid range: 1 - 7
58   div-p2:
62         Valid range: 1 - 7